openpower/sv/rfc/ls011.mdwn

   1 # RFC ls011 LD/ST-Update-PostIncrement
   2
   3 **URLs**:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls011/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/TODO>
   9
  10 **Severity**: Major
  11
  12 **Status**: New
  13
  14 **Date**: 21 Apr 2023.
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.0B
  19
  20 **Books and Section affected**:
  21
  22 ```
  23     Chapter 2 Book I, new Fixed-Point Load / Store Sections 3.3.2 3.3.3
  24     Chapter 4 Book I, new Floating-Point Load / Store Sections 4.6.2 4.6.3
  25 ```
  26
  27 **Summary**
  28
  29 ```
  30     TODO
  31 ```
  32
  33 **Submitter**: Luke Leighton (Libre-SOC)
  34
  35 **Requester**: Libre-SOC
  36
  37 **Impact on processor**:
  38
  39 ```
  40     TODO
  41 ```
  42
  43 **Impact on software**:
  44
  45 ```
  46     Requires support for new instructions in assembler, debuggers, and related tools.
  47     Reduces instructions in hot-loops
  48 ```
  49
  50 **Keywords**:
  51
  52 ```
  53
  54 ```
  55
  56 **Motivation**
  57
  58
  59
  60 **Notes and Observations**:
  61
  62
  63
  64 **Changes**
  65
  66 Add the following entries to:
  67
  68 * A new "Vector Looping" Book
  69 * New Vector-Looping Chapters
  70 * New Vector-Looping Appendices
  71
  72 [[!tag opf_rfc]]
  73
  74 --------
  75
  76 \newpage{}
  77
  78 TODO (key stub notes below)
  79
  80
  81
  82 The following instructions are proposed to be added in EXT2xx,
  83 duplicating LD/ST-Update functionality but moving the update
  84 of RA to *after* the Memory operation.  These types of
  85 instructions are already present in x86 (sort-of).
  86
  87 * x86 chose that store should be pre-indexed and load should be post-indexed
  88 * Power ISA chose everything to be pre-indexed
  89 * Motorola 68000 (decades old) has pre- and post- indexed
  90
  91 <https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
  92
  93 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
  94
  95 The LD/ST-Immediate-Post-Increment instructions are all Primary
  96 Opcode: there are 13 of these.  LD/ST-Indexed-Post-Increment
  97 are all effectively 9-bit XO and consequently may easily
  98 fit into one single Primary Opcode.  EXT2xx is recommended.
  99
 100 One alternative idea is that bit 31 could be allocated (retrospectively)
 101 to Post-Increment.  Although it may be too late for Scalar Power ISA
 102 it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
 103 but this risks creating a non-Orthogonal ISA.
 104
 105
 106
 107 ```
 108 # LD/ST-Postincrement
 109 lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 110 lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 111 lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 112 lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 113 lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 114 lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 115 lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 116 lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 117 lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 118 ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 119 ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 120 stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 121 stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 122 sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 123 sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 124 stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 125 stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 126 stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 127 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 128
 129 # FP LD/ST-Postincrement
 130 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 131 lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 132 lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 133 lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
 134 stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 135 stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 136 stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 137 stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 138
 139 # LD/ST-Shifted-Postincrement
 140 lbzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 141 lhzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 142 lhauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 143 lwzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 144 lwauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 145 lduspx,    ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 146 stbuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 147 sthuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 148 stwuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 149 stduspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 150
 151 # FP LD/ST-Shifted-Postincrement
 152 lfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 153 lfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
 154 stfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 155 stfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
 156
 157 ```
 158
 159 # Example
 160
 161 Here is an annotated example where the pseudo-code changes to
 162 just use `RA` as the address, otherwise remaining the same.
 163 No actual change to the Effective Address computation itself
 164 occurs, in any of the Post-Update instructions.
 165
 166 ** Load Byte and Zero with Post-Update**
 167
 168 D-Form
 169
 170 * lbzup RT,D(RA)
 171
 172 Pseudo-code:
 173
 174 ```
 175     EA <- (RA)                           # EA just RA
 176     RT <- ([0] * (XLEN-8)) || MEM(EA, 1) # then load
 177     RA <- (RA) + EXTS(D)                 # then update RA after
 178 ```
 179
 180 Special Registers Altered:
 181
 182 ```
 183     None
 184 ```
 185
 186 where the same pseudocode for `lbzu` is:
 187
 188 ```
 189     EA <- (RA) + EXTS(D)                  # EA includes D
 190     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)  # load from RA+D
 191     RA <- EA                              # and update RA
 192 ```
 193 -----
 194
 195 \newpage{}
 196
 197 # Fixed-point Load with Post-Update
 198
 199 Add the following additional Section to Fixed-Point Load Book I
 200
 201 ## Load Byte and Zero with Post-Update
 202
 203 D-Form
 204
 205 * lbzup RT,D(RA)
 206
 207 Pseudo-code:
 208
 209     EA <- (RA)
 210     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 211     RA <- (RA) + EXTS(D)
 212
 213 Special Registers Altered:
 214
 215     None
 216
 217 ## Load Byte and Zero with Post-Update Indexed
 218
 219 X-Form
 220
 221 * lbzupx RT,RA,RB
 222
 223 Pseudo-code:
 224
 225     EA <- (RA)
 226     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 227     RA <- (RA) + (RB)
 228
 229 Special Registers Altered:
 230
 231     None
 232
 233 ## Load Halfword and Zero with Post-Update
 234
 235 D-Form
 236
 237 * lhzup RT,D(RA)
 238
 239 Pseudo-code:
 240
 241     EA <- (RA)
 242     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 243     RA <- (RA) + EXTS(D)
 244
 245 Special Registers Altered:
 246
 247     None
 248
 249 ## Load Halfword and Zero with Post-Update Indexed
 250
 251 X-Form
 252
 253 * lhzupx RT,RA,RB
 254
 255 Pseudo-code:
 256
 257     EA <- (RA)
 258     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 259     RA <- (RA) + (RB)
 260
 261 Special Registers Altered:
 262
 263     None
 264
 265 ## Load Halfword Algebraic with Post-Update
 266
 267 D-Form
 268
 269 * lhaup RT,D(RA)
 270
 271 Pseudo-code:
 272
 273     EA <- (RA)
 274     RT <- EXTS(MEM(EA, 2))
 275     RA <- (RA) + EXTS(D)
 276
 277 Special Registers Altered:
 278
 279     None
 280
 281 ## Load Halfword Algebraic with Post-Update Indexed
 282
 283 X-Form
 284
 285 * lhaupx RT,RA,RB
 286
 287 Pseudo-code:
 288
 289     EA <- (RA)
 290     RT <- EXTS(MEM(EA, 2))
 291     RA <- (RA) + (RB)
 292
 293 Special Registers Altered:
 294
 295     None
 296
 297 ## Load Word and Zero with Post-Update
 298
 299 D-Form
 300
 301 * lwzup RT,D(RA)
 302
 303 Pseudo-code:
 304
 305     EA <- (RA)
 306     RT <- [0]*32 || MEM(EA, 4)
 307     RA <- (RA) + EXTS(D)
 308
 309 Special Registers Altered:
 310
 311     None
 312
 313 ## Load Word and Zero with Post-Update Indexed
 314
 315 X-Form
 316
 317 * lwzupx RT,RA,RB
 318
 319 Pseudo-code:
 320
 321     EA <- (RA)
 322     RT <- [0] * 32 || MEM(EA, 4)
 323     RA <- (RA) + (RB)
 324
 325 Special Registers Altered:
 326
 327     None
 328
 329 ## Load Word Algebraic with Post-Update Indexed
 330
 331 X-Form
 332
 333 * lwaupx RT,RA,RB
 334
 335 Pseudo-code:
 336
 337     EA <- (RA)
 338     RT <- EXTS(MEM(EA, 4))
 339     RA <- (RA) + (RB)
 340
 341 Special Registers Altered:
 342
 343     None
 344
 345 ## Load Doubleword with Post-Update Indexed
 346
 347 DS-Form
 348
 349 * ldup RT,DS(RA)
 350
 351 Pseudo-code:
 352
 353     EA <- (RA)
 354     RT <- MEM(EA, 8)
 355     RA <- (RA) + EXTS(DS || 0b00)
 356
 357 Special Registers Altered:
 358
 359     None
 360
 361 ## Load Doubleword with Post-Update Indexed
 362
 363 X-Form
 364
 365 * ldupx RT,RA,RB
 366
 367 Pseudo-code:
 368
 369     EA <- (RA)
 370     RT <- MEM(EA, 8)
 371     RA <- (RA) + (RB)
 372
 373 Special Registers Altered:
 374
 375     None
 376
 377 -----
 378
 379 \newpage{}
 380
 381 # Fixed-Point Store Post-Update
 382
 383 Add the following as a new section in Fixed-Point Store, Book I
 384
 385 ## Store Byte with Update
 386
 387 D-Form
 388
 389 * stbup RS,D(RA)
 390
 391 Pseudo-code:
 392
 393     EA <- (RA) + EXTS(D)
 394     ea <- (RA)
 395     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
 396     RA <- EA
 397
 398 Special Registers Altered:
 399
 400     None
 401
 402 ## Store Byte with Update Indexed
 403
 404 X-Form
 405
 406 * stbupx RS,RA,RB
 407
 408 Pseudo-code:
 409
 410     EA <- (RA) + (RB)
 411     ea <- (RA)
 412     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
 413     RA <- EA
 414
 415 Special Registers Altered:
 416
 417     None
 418
 419 ## Store Halfword with Update
 420
 421 D-Form
 422
 423 * sthup RS,D(RA)
 424
 425 Pseudo-code:
 426
 427     EA <- (RA) + EXTS(D)
 428     ea <- (RA)
 429     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
 430     RA <- EA
 431
 432 Special Registers Altered:
 433
 434     None
 435
 436 ## Store Halfword with Update Indexed
 437
 438 X-Form
 439
 440 * sthupx RS,RA,RB
 441
 442 Pseudo-code:
 443
 444     EA <- (RA) + (RB)
 445     ea <- (RA)
 446     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
 447     RA <- EA
 448
 449 Special Registers Altered:
 450
 451     None
 452
 453 ## Store Word with Update
 454
 455 D-Form
 456
 457 * stwup RS,D(RA)
 458
 459 Pseudo-code:
 460
 461     EA <- (RA) + EXTS(D)
 462     ea <- (RA)
 463     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 464     RA <- EA
 465
 466 Special Registers Altered:
 467
 468     None
 469
 470 ## Store Word with Update Indexed
 471
 472 X-Form
 473
 474 * stwupx RS,RA,RB
 475
 476 Pseudo-code:
 477
 478     EA <- (RA) + (RB)
 479     ea <- (RA)
 480     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 481     RA <- EA
 482
 483 Special Registers Altered:
 484
 485     None
 486
 487 ## Store Doubleword with Update
 488
 489 DS-Form
 490
 491 * stdup RS,DS(RA)
 492
 493 Pseudo-code:
 494
 495     EA <- (RA) + EXTS(DS || 0b00)
 496     ea <- (RA)
 497     MEM(ea, 8) <- (RS)
 498     RA <- EA
 499
 500 Special Registers Altered:
 501
 502     None
 503
 504 ## Store Doubleword with Update Indexed
 505
 506 X-Form
 507
 508 * stdupx RS,RA,RB
 509
 510 Pseudo-code:
 511
 512     EA <- (RA) + (RB)
 513     ea <- (RA)
 514     MEM(ea, 8) <- (RS)
 515     RA <- EA
 516
 517 Special Registers Altered:
 518
 519     None
 520
 521 [[!tag opf_rfc]]