1 # LD/ST-Update-PostIncrement
3 TODO (key stub notes below)
5 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
7 The following instructions are proposed to be added in EXT2xx,
8 duplicating LD/ST-Update functionality but moving the update
9 of RA to *after* the Memory operation. These types of
10 instructions are already present in x86 (sort-of).
12 * x86 chose that store should be pre-indexed and load should be post-indexed
13 * Power ISA chose everything to be pre-indexed
14 * Motorola 68000 (decades old) has pre- and post- indexed
16 <https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>
18 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
20 The LD/ST-Immediate-Post-Increment instructions are all Primary
21 Opcode: there are 13 of these. LD/ST-Indexed-Post-Increment
22 are all effectively 9-bit XO and consequently may easily
23 fit into one single Primary Opcode. EXT2xx is recommended.
25 One alternative idea is that bit 31 could be allocated (retrospectively)
26 to Post-Increment. Although it may be too late for Scalar Power ISA
27 it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
28 but this risks creating a non-Orthogonal ISA.
34 lbzup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
35 lbzupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
36 lhzup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
37 lhzupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
38 lhaup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
39 lhaupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
40 lwzup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
41 lwzupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
42 lwaupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
43 ldup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
44 ldupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
45 stbup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
46 stbupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
47 sthup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
48 sthupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
49 stwup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
50 stwupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
51 stdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
52 stdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
54 # FP LD/ST-Postincrement
55 lfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
56 lfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
57 lfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
58 lsdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
59 stfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
60 stfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
61 stfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
62 stfsux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
64 # LD/ST-Shifted-Postincrement
65 lbzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
66 lhzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
67 lhauspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
68 lwzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
69 lwauspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
70 lduspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
71 stbuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
72 sthuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
73 stwuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
74 stduspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
76 # FP LD/ST-Shifted-Postincrement
77 lfdupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
78 lfsupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
79 stfdupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
80 stfsupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
86 Here is an annotated example where the pseudo-code changes to
87 just use `RA` as the address, otherwise remaining the same.
88 No actual change to the Effective Address computation itself
89 occurs, in any of the Post-Update instructions.
91 ** Load Byte and Zero with Post-Update**
100 EA <- (RA) # EA just RA
101 RT <- ([0] * (XLEN-8)) || MEM(EA, 1) # then load
102 RA <- (RA) + EXTS(D) # then update RA after
105 Special Registers Altered:
111 where the same pseudocode for `lbzu` is:
114 EA <- (RA) + EXTS(D) # EA includes D
115 RT <- ([0] * (XLEN-8)) || MEM(EA, 1) # load from RA+D
116 RA <- EA # and update RA
122 # Fixed-point Load with Post-Update
124 Add the following additional Section to Fixed-Point Load Book I
126 ## Load Byte and Zero with Post-Update
135 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
138 Special Registers Altered:
142 ## Load Byte and Zero with Post-Update Indexed
151 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
154 Special Registers Altered:
158 ## Load Halfword and Zero with Post-Update
167 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
170 Special Registers Altered:
174 ## Load Halfword and Zero with Post-Update Indexed
183 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
186 Special Registers Altered:
190 ## Load Halfword Algebraic with Post-Update
199 RT <- EXTS(MEM(EA, 2))
202 Special Registers Altered:
206 ## Load Halfword Algebraic with Post-Update Indexed
215 RT <- EXTS(MEM(EA, 2))
218 Special Registers Altered:
222 ## Load Word and Zero with Post-Update
231 RT <- [0]*32 || MEM(EA, 4)
234 Special Registers Altered:
238 ## Load Word and Zero with Post-Update Indexed
247 RT <- [0] * 32 || MEM(EA, 4)
250 Special Registers Altered:
254 ## Load Word Algebraic with Post-Update Indexed
263 RT <- EXTS(MEM(EA, 4))
266 Special Registers Altered:
270 ## Load Doubleword with Post-Update Indexed
280 RA <- (RA) + EXTS(DS || 0b00)
282 Special Registers Altered:
286 ## Load Doubleword with Post-Update Indexed
298 Special Registers Altered: