openpower/sv/rfc/ls013.mdwn

   1 # RFC ls013 Min/Max GPR/FPR
   2
   3 * Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
   4   Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
   5 * <https://libre-soc.org/openpower/sv/rfc/ls013/>
   6 * <https://git.openpower.foundation/isa/PowerISA/issues/TODO>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1057>
   8
   9 **Severity**: Major
  10
  11 **Status**: New
  12
  13 **Date**: 14 Apr 2023
  14
  15 **Target**: v3.2B
  16
  17 **Source**: v3.1B
  18
  19 **Books and Section affected**:
  20
  21 ```
  22     Book I Fixed-Point and Floating-Point Instructions
  23     Appendix E Power ISA sorted by opcode
  24     Appendix F Power ISA sorted by version
  25     Appendix G Power ISA sorted by Compliancy Subset
  26     Appendix H Power ISA sorted by mnemonic
  27 ```
  28
  29 **Summary**
  30
  31 ```
  32     Instructions added
  33 ```
  34
  35 **Submitter**: Luke Leighton (Libre-SOC)
  36
  37 **Requester**: Libre-SOC
  38
  39 **Impact on processor**:
  40
  41 ```
  42     Addition of new GPR-based and FPR-based instructions
  43 ```
  44
  45 **Impact on software**:
  46
  47 ```
  48     Requires support for new instructions in assembler, debuggers,
  49     and related tools.
  50 ```
  51
  52 **Keywords**:
  53
  54 ```
  55     GPR, FPR, min, max, fmin, fmax
  56 ```
  57
  58 **Motivation**
  59
  60 Minimum/Maximum are common operations that can take an astounding number of
  61 operations to implement in software. Additionally, Vector Reduce-Min/Max are
  62 common vector operations, and SVP64 Parallel Reduction needs a single Scalar
  63 instruction in order to effectively implement Reduce-Min/Max.
  64
  65 **Notes and Observations**:
  66
  67 1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to
  68     work with, for best effectiveness.  With no SFFS minimum/maximum
  69     instructions Simple-V min/max Parallel Reduction is severely compromised.
  70 2. Once one FP min/max mode is implemented the rest are not much more hardware.
  71 3. There exists similar instructions in VSX (not IEEE754-2019 though).
  72     This is frequently used to justify not adding them. However SVP64/VSX may
  73     have different meaning from SVP64/SFFS, so it is *really* crucial to have
  74     SFFS ops even if "equivalent" to VSX in order for SVP64 to not be
  75     compromised (non-orthogonal).
  76 4. FP min/max are rather complex to implement in software, the most commonly
  77     used FP max function `fmax` from glibc compiled for SFFS is an astounding
  78     32 instructions.
  79
  80 **Changes**
  81
  82 Add the following entries to:
  83
  84 * the Appendices of Book I
  85 * Book I 3.3.9 Fixed-Point Arithmetic Instructions
  86 * Book I 4.6.6.1 Floating-Point Elementary Arithmetic Instructions
  87 * Book I 1.6.1 and 1.6.2
  88
  89 ----------------
  90
  91 \newpage{}
  92
  93 # Floating-Point Instructions
  94
  95 This group is to provide Floating-Point min/max, however with the 2019 version
  96 of IEEE 754 there are now subtle differences. These are selectable with a
  97 Mode Field, `FMM`.
  98
  99 ## `FMM` -- Floating Min/Max Mode
 100
 101 <a id="fmm-floating-min-max-mode"></a>
 102
 103 <!-- hyphens in table determine width of columns for pandoc -- -->
 104 | `FMM`| Extended Mnemonic             | Origin             | Semantics                                  |
 105 |------|-------------------------------|--------------------|--------------------------------------------|
 106 | 0000 | fminnum08[s] FRT,FRA,FRB      | IEEE 754-2008      | minNum(FRA,FRB)  (1)                       |
 107 | 0001 | fmin19[s] FRT,FRA,FRB         | IEEE 754-2019      | minimum(FRA,FRB)                           |
 108 | 0010 | fminnum19[s] FRT,FRA,FRB      | IEEE 754-2019      | minimumNumber(FRA,FRB)                     |
 109 | 0011 | fminc[s] FRT,FRA,FRB          | x86 minss (4)      | FRA\<FRB ? FRA:FRB                      |
 110 | 0100 | fminmagnum08[s] FRT,FRA,FRB   | IEEE 754-2008 (3)  | mmmag(FRA,FRB,False,fminnum08) (2)   |
 111 | 0101 | fminmag19[s] FRT,FRA,FRB      | IEEE 754-2019      | mmmag(FRA,FRB,False,fmin19) (2)      |
 112 | 0110 | fminmagnum19[s] FRT,FRA,FRB   | IEEE 754-2019      | mmmag(FRA,FRB,False,fminnum19) (2)   |
 113 | 0111 | fminmagc[s] FRT,FRA,FRB       | -                  | mmmag(FRA,FRB,False,fminc) (2)       |
 114 | 1000 | fmaxnum08[s] FRT,FRA,FRB      | IEEE 754-2008      | maxNum(FRA,FRB)  (1)                       |
 115 | 1001 | fmax19[s] FRT,FRA,FRB         | IEEE 754-2019      | maximum(FRA,FRB)                           |
 116 | 1010 | fmaxnum19[s] FRT,FRA,FRB      | IEEE 754-2019      | maximumNumber(FRA,FRB)                     |
 117 | 1011 | fmaxc[s] FRT,FRA,FRB          | x86 maxss (4)      | FRA\>FRB ? FRA:FRB                       |
 118 | 1100 | fmaxmagnum08[s] FRT,FRA,FRB   | IEEE 754-2008 (3)  | mmmag(FRA,FRB,True,fmaxnum08) (2)    |
 119 | 1101 | fmaxmag19[s] FRT,FRA,FRB      | IEEE 754-2019      | mmmag(FRA,FRB,True,fmax19) (2)       |
 120 | 1110 | fmaxmagnum19[s] FRT,FRA,FRB   | IEEE 754-2019      | mmmag(FRA,FRB,True,fmaxnum19) (2)    |
 121 | 1111 | fmaxmagc[s] FRT,FRA,FRB       | -                  | mmmag(FRA,FRB,True,fmaxc) (2)        |
 122
 123 Note (1): for the purposes of minNum/maxNum, -0.0 is defined to be less than
 124     +0.0. This is left unspecified in IEEE 754-2008.
 125
 126 Note (2): mmmag(x, y, cmp, fallback) is defined as:
 127
 128 ```python
 129 def mmmag(x, y, is_max, fallback):
 130     a = abs(x) < abs(y)
 131     b = abs(x) > abs(y)
 132     if is_max:
 133         a, b = b, a  # swap
 134     if a:
 135         return x
 136     if b:
 137         return y
 138     # equal magnitudes, or NaN input(s)
 139     return fallback(x, y)
 140 ```
 141
 142 Note (3): TODO: icr if IEEE 754-2008 has min/maxMagNum like IEEE 754-2019's
 143     minimum/maximumMagnitudeNumber
 144
 145 Note (4) or Win32's min macro
 146
 147 ----------------
 148
 149 \newpage{}
 150
 151 ## Floating Minimum/Maximum MM-form
 152
 153 * fminmax FRT, FRA, FRB, FMM
 154 * fminmax. FRT, FRA, FRB, FMM
 155
 156 ```
 157     |0    |6    |11   |16   |21   |25  |31  |
 158     | PO  | FRT | FRA | FRB | FMM | XO | Rc |
 159 ```
 160
 161 ```
 162     result <- [0] * 64
 163     a <- (FRA)
 164     b <- (FRB)
 165     abs_a <- 0b0 || a[1:63]
 166     abs_b <- 0b0 || b[1:63]
 167     a_is_nan <- abs_a >u 0x7FF0_0000_0000_0000
 168     a_is_snan <- a_is_nan & (a[12] = 0)
 169     b_is_nan <- abs_b >u 0x7FF0_0000_0000_0000
 170     b_is_snan <- b_is_nan & (b[12] = 0)
 171     any_snan <- a_is_snan | b_is_snan
 172     a_quieted <- a
 173     a_quieted[12] <- 1
 174     b_quieted <- b
 175     b_quieted[12] <- 1
 176     if a_is_nan | b_is_nan then
 177         if FMM[2:3] = 0b00 then  # min/maxnum08
 178             if a_is_snan then result <- a_quieted
 179             else if b_is_snan then result <- b_quieted
 180             else if a_is_nan & b_is_nan then result <- a_quieted
 181             else if a_is_nan then result <- b
 182             else result <- a
 183         if FMM[2:3] = 0b01 then  # min/max19
 184             if a_is_nan then result <- a_quieted
 185             else result <- b_quieted
 186         if FMM[2:3] = 0b10 then  # min/maxnum19
 187             if a_is_nan & b_is_nan then result <- a_quieted
 188             else if a_is_nan then result <- b
 189             else result <- a
 190         if FMM[2:3] = 0b11 then  # min/maxc
 191             result <- b
 192     else
 193         cmp_l <- a
 194         cmp_r <- b
 195         if FMM[1] then  # min/maxmag
 196             if abs_a != abs_b then
 197                 cmp_l <- abs_a
 198                 cmp_r <- abs_b
 199         if FMM[2:3] = 0b11 then  # min/maxc
 200             if abs_a = 0 then cmp_l[0:63] <- 0
 201             if abs_b = 0 then cmp_r[0:63] <- 0
 202         if FMM[0] then  # max
 203             # swap cmp_* so comparison goes the other way
 204             cmp_l, cmp_r <- cmp_r, cmp_l
 205         if cmp_l[0] = 1 then
 206             if cmp_r[0] = 0 then result <- a
 207             else if cmp_l >u cmp_r then
 208                 # IEEE 754 is sign-magnitude,
 209                 # so bigger magnitude negative is smaller
 210                 result <- a
 211             else result <- b
 212         else if cmp_r[0] = 1 then result <- b
 213         else if cmp_l <u cmp_r then result <- a
 214         else result <- b
 215     if any_snan then SetFX(FPSCR.VXSNAN)
 216     if (FPSCR.VE = 0) | ¬any_snan then (FRT) <- result
 217 ```
 218
 219 Compute the minimum/maximum of FRA and FRB, according to FMM, and store the
 220 result in FRT.
 221
 222 Special Registers altered:
 223
 224 ```
 225     FX VXSNAN
 226     CR1     (if Rc=1)
 227 ```
 228
 229 Extended Mnemonics:
 230
 231 see [`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode)
 232
 233 ----------
 234
 235 # Fixed-Point Instructions
 236
 237 These are signed and unsigned, min or max.  SVP64 Prefixing defines Saturation
 238 semantics therefore Saturated variants of these instructions need not be proposed.
 239
 240 ## `MMM` -- Integer Min/Max Mode
 241
 242 <a id="mmm-integer-min-max-mode"></a>
 243
 244 * bit 0: set if word variant else dword
 245 * bit 1: set if signed else unsigned
 246 * bit 2: set if max else min
 247
 248 | `MMM` | Extended Mnemonic | Semantics                                    |
 249 |-------|-------------------|----------------------------------------------|
 250 | 000   | `minu RT,RA,RB`   | `(uint64_t)RA < (uint64_t)RB ? RA : RB` |
 251 | 001   | `maxu RT,RA,RB`   | `(uint64_t)RA > (uint64_t)RB ? RA : RB` |
 252 | 010   | `mins RT,RA,RB`   | ` (int64_t)RA < (int64_t)RB  ? RA : RB` |
 253 | 011   | `maxs RT,RA,RB`   | ` (int64_t)RA > (int64_t)RB  ? RA : RB` |
 254 | 100   | `minuw RT,RA,RB`  | `(uint32_t)RA < (uint32_t)RB ? RA : RB` |
 255 | 101   | `maxuw RT,RA,RB`  | `(uint32_t)RA > (uint32_t)RB ? RA : RB` |
 256 | 110   | `minsw RT,RA,RB`  | ` (int32_t)RA < (int32_t)RB  ? RA : RB` |
 257 | 111   | `maxsw RT,RA,RB`  | ` (int32_t)RA > (int32_t)RB  ? RA : RB` |
 258
 259 ## Minimum/Maximum MM-Form
 260
 261 * minmax RT, RA, RB, MMM
 262 * minmax. RT, RA, RB, MMM
 263
 264 ```
 265     |0    |6    |11   |16   |21   |24 |25  |31  |
 266     | PO  | RT  | RA  | RB  | MMM | / | XO | Rc |
 267 ```
 268
 269 ```
 270     a <- (RA|0)
 271     b <- (RB)
 272     if MMM[0] then  # word mode
 273         # shift left by XLEN/2 to make the dword comparison
 274         # do word comparison of the original inputs
 275         a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
 276         b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
 277     if MMM[1] then  # signed mode
 278         # invert sign bits to make the unsigned comparison
 279         # do signed comparison of the original inputs
 280         a[0] <- ¬a[0]
 281         b[0] <- ¬b[0]
 282     # if Rc = 1 then store the result of comparing a and b to CR0
 283     if Rc = 1 then
 284         if a <u b then
 285             CR0 <- 0b100 || XER.SO
 286         if a = b then
 287             CR0 <- 0b001 || XER.SO
 288         if a >u b then
 289             CR0 <- 0b010 || XER.SO
 290     if MMM[2] then  # max mode
 291         # swap a and b to make the less than comparison do
 292         # greater than comparison of the original inputs
 293         t <- a
 294         a <- b
 295         b <- t
 296     # store the entire selected source (even in word mode)
 297     # if Rc = 1 then store the result of comparing a and b to CR0
 298     if a <u b then RT <- (RA|0)
 299     else RT <- (RB)
 300 ```
 301
 302 Compute the integer minimum/maximum according to `MMM` of `(RA|0)` and `(RB)`
 303 and store the result in `RT`.
 304
 305 Special Registers altered:
 306
 307 ```
 308     CR0     (if Rc=1)
 309 ```
 310
 311 Extended Mnemonics:
 312
 313 see [`MMM` -- Integer Min/Max Mode](#mmm-integer-min-max-mode)
 314
 315 ----------
 316
 317 \newpage{}
 318
 319 # Instruction Formats
 320
 321 Add the following entries to Book I 1.6.1 Word Instruction Formats:
 322
 323 ## MM-FORM
 324
 325 ```
 326     |0    |6    |11   |16   |21   |24 |25  |31  |
 327     | PO  | FRT | FRA | FRB | FMM     | XO | Rc |
 328     | PO  | RT  | RA  | RB  | MMM | / | XO | Rc |
 329 ```
 330
 331 Add the following new fields to Book I 1.6.2 Word Instruction Fields:
 332
 333 ```
 334     FMM (21:24)
 335         Field used to specify minimum/maximum mode for fminmax.
 336
 337         Formats: MM
 338
 339     MMM (21:23)
 340         Field used to specify minimum/maximum mode for integer minmax.
 341
 342         Formats: MM
 343 ```
 344
 345 Add `MM` to the `Formats:` list for all of `FRT`, `FRA`, `FRB`, `XO (25:30)`,
 346 `Rc`, `RT`, `RA` and `RB`.
 347
 348 ----------
 349
 350 \newpage{}
 351
 352 # Appendices
 353
 354     Appendix E Power ISA sorted by opcode
 355     Appendix F Power ISA sorted by version
 356     Appendix G Power ISA sorted by Compliancy Subset
 357     Appendix H Power ISA sorted by mnemonic
 358
 359 | Form | Book | Page | Version | Mnemonic | Description |
 360 |------|------|------|---------|----------|-------------|
 361 | MM   | I    | #    | 3.2B    | fminmax  | Floating Minimum/Maximum |
 362 | MM   | I    | #    | 3.2B    | minmax   | Minimum/Maximum |
 363
 364 ## fmax instruction count
 365
 366 32 instructions are required in SFFS to emulate fmax.
 367
 368 ```
 369     #include <stdint.h>
 370     #include <string.h>
 371
 372     inline uint64_t asuint64(double f) {
 373         union {
 374             double f;
 375             uint64_t i;
 376         } u = {f};
 377         return u.i;
 378     }
 379
 380     inline int issignaling(double v) {
 381         // copied from glibc:
 382         // https://github.com/bminor/glibc/blob/e2756903/sysdeps/ieee754/dbl-64/math_config.h#L101
 383         uint64_t ix = asuint64(v);
 384         return 2 * (ix ^ 0x0008000000000000) > 2 * 0x7ff8000000000000ULL;
 385     }
 386
 387     double fmax(double x, double y) {
 388         // copied from glibc:
 389         // https://github.com/bminor/glibc/blob/e2756903/math/s_fmax_template.c
 390         if(__builtin_isgreaterequal(x, y))
 391             return x;
 392         else if(__builtin_isless(x, y))
 393             return y;
 394         else if(issignaling(x) || issignaling(y))
 395             return x + y;
 396         else
 397             return __builtin_isnan(y) ? x : y;
 398     }
 399 ```
 400
 401 Assembly listing:
 402
 403 ```
 404     fmax(double, double):
 405         fcmpu 0,1,2
 406         fmr 0,1
 407         cror 30,1,2
 408         beq 7,.L12
 409         blt 0,.L13
 410         stfd 1,-16(1)
 411         lis 9,0x8
 412         li 8,-1
 413         sldi 9,9,32
 414         rldicr 8,8,0,11
 415         ori 2,2,0
 416         ld 10,-16(1)
 417         xor 10,10,9
 418         sldi 10,10,1
 419         cmpld 0,10,8
 420         bgt 0,.L5
 421         stfd 2,-16(1)
 422         ori 2,2,0
 423         ld 10,-16(1)
 424         xor 9,10,9
 425         sldi 9,9,1
 426         cmpld 0,9,8
 427         ble 0,.L6
 428 .L5:
 429         fadd 1,0,2
 430         blr
 431 .L13:
 432         fmr 1,2
 433         blr
 434 .L6:
 435         fcmpu 0,2,2
 436         fmr 1,2
 437         bnulr 0
 438 .L12:
 439         fmr 1,0
 440         blr
 441         .long 0
 442         .byte 0,9,0,0,0,0,0,0
 443 ```
 444
 445 [[!tag opf_rfc]]
 446