1 # RFC ls013 Min/Max GPR/FPR
5 * <https://libre-soc.org/openpower/sv/rfc/ls013/>
6 * <https://git.openpower.foundation/isa/PowerISA/issues/TODO>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1057>
19 **Books and Section affected**:
22 Book I Fixed-Point and Floating-Point Instructions
23 Appendix E Power ISA sorted by opcode
24 Appendix F Power ISA sorted by version
25 Appendix G Power ISA sorted by Compliancy Subset
26 Appendix H Power ISA sorted by mnemonic
35 **Submitter**: Luke Leighton (Libre-SOC)
37 **Requester**: Libre-SOC
39 **Impact on processor**:
42 Addition of new GPR-based and FPR-based instructions
45 **Impact on software**:
48 Requires support for new instructions in assembler, debuggers,
55 GPR, FPR, min, max, fmin, fmax
62 **Notes and Observations**:
64 1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to
65 work with, for best effectiveness. With no SFFS minimum/maximum instructions
66 Simple-V min/max Parallel Reduction is severely compromised.
67 2. Once one FP min/max mode is implemented the rest are not much more
69 3. There exists similar instructions in VSX (not IEEE754-2019 though).
70 This is frequently used to justify not
71 adding them. However SVP64/VSX may have different meaning from SVP64/SFFS,
72 so it is *really* crucial to have SFFS ops even if "equivalent" to VSX
73 in order for SVP64 to not be compromised (non-orthogonal).
74 4. FP min/max are rather complex to implement in software, the most commonly
75 used FP max function `fmax` from glibc compiled for SFFS is an
76 astounding 32 instructions.
80 Add the following entries to:
82 * the Appendices of Book I
83 * Book I 3.3.9 Fixed-Point Arithmetic Instructions
84 * Book I 4.6.6.1 Floating-Point Elementary Arithmetic Instructions
85 * Book I 1.6.1 and 1.6.2
91 # Floating-Point Instructions
93 This group is to provide Floating-Point min/max however with IEEE754 having advanced
94 to 2019 there are now subtle differences. These are selectable with a Mode Field, `FMM`.
96 ## `FMM` -- Floating Min/Max Mode
98 <a id="fmm-floating-min-max-mode"></a>
100 | `FMM` | Assembly Alias | Origin | Semantics |
101 |-------|-------------------------------|--------------------------------|-------------------------------------------------|
102 | 0000 | fminnum08[s] FRT, FRA, FRB | IEEE 754-2008 | FRT = minNum(FRA, FRB) (1) |
103 | 0001 | fmin19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minimum(FRA, FRB) |
104 | 0010 | fminnum19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minimumNumber(FRA, FRB) |
105 | 0011 | fminc[s] FRT, FRA, FRB | x86 minss or Win32's min macro | FRT = FRA \< FRB ? FRA : FRB |
106 | 0100 | fminmagnum08[s] FRT, FRA, FRB | IEEE 754-2008 (TODO: (3)) | FRT = minmaxmag(FRA, FRB, False, fminnum08) (2) |
107 | 0101 | fminmag19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minmaxmag(FRA, FRB, False, fmin19) (2) |
108 | 0110 | fminmagnum19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minmaxmag(FRA, FRB, False, fminnum19) (2) |
109 | 0111 | fminmagc[s] FRT, FRA, FRB | - | FRT = minmaxmag(FRA, FRB, False, fminc) (2) |
110 | 1000 | fmaxnum08[s] FRT, FRA, FRB | IEEE 754-2008 | FRT = maxNum(FRA, FRB) (1) |
111 | 1001 | fmax19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = maximum(FRA, FRB) |
112 | 1010 | fmaxnum19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = maximumNumber(FRA, FRB) |
113 | 1011 | fmaxc[s] FRT, FRA, FRB | x86 maxss or Win32's max macro | FRT = FRA > FRB ? FRA : FRB |
114 | 1100 | fmaxmagnum08[s] FRT, FRA, FRB | IEEE 754-2008 (TODO: (3)) | FRT = minmaxmag(FRA, FRB, True, fmaxnum08) (2) |
115 | 1101 | fmaxmag19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minmaxmag(FRA, FRB, True, fmax19) (2) |
116 | 1110 | fmaxmagnum19[s] FRT, FRA, FRB | IEEE 754-2019 | FRT = minmaxmag(FRA, FRB, True, fmaxnum19) (2) |
117 | 1111 | fmaxmagc[s] FRT, FRA, FRB | - | FRT = minmaxmag(FRA, FRB, True, fmaxc) (2) |
119 Note (1): for the purposes of minNum/maxNum, -0.0 is defined to be less than
120 +0.0. This is left unspecified in IEEE 754-2008.
122 Note (2): minmaxmag(x, y, cmp, fallback) is defined as:
125 def minmaxmag(x, y, is_max, fallback):
134 # equal magnitudes, or NaN input(s)
135 return fallback(x, y)
138 Note (3): TODO: icr if IEEE 754-2008 has min/maxMagNum like IEEE 754-2019's
139 minimum/maximumMagnitudeNumber
145 ## Floating Minimum/Maximum
150 * fminmax FRT, FRA, FRB, FMM
151 * fminmax. FRT, FRA, FRB, FMM
154 |0 |6 |11 |16 |21 |26 |31 |
155 | PO | FRT | FRA | FRB | FMM[0:3] / | XO | Rc |
158 Special Registers altered:
164 Compute the minimum/maximum of FRA and FRB, according to FMM, and store the
167 Assembly Aliases: see
168 [`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode)
172 ## Floating Minimum/Maximum Single
176 * fminmaxs FRT, FRA, FRB, FMM
177 * fminmaxs. FRT, FRA, FRB, FMM
180 |0 |6 |11 |16 |21 |26 |31 |
181 | PO | FRT | FRA | FRB | FMM[0:3] / | XO | Rc |
184 Special Registers altered:
192 Compute the minimum/maximum of FRA and FRB, according to FMM, and store the
195 Assembly Aliases: see
196 [`FMM` -- Floating Min/Max Mode](#fmm-floating-min-max-mode)
202 # Fixed-Point Instructions
204 These are signed and unsigned, min or max. SVP64 Prefixing defines Saturation
205 semantics therefore Saturated variants of these instructions need not be proposed.
207 ## Integer MinMax Mode
209 * bit 0: set if word variant else dword
210 * bit 1: set if signed else unsigned
211 * bit 2: set if max else min
213 | `IMM` | Assembly Alias |
214 |-------|--------------------|
215 | 000 | minu RT,RA,RB |
216 | 001 | maxu RT,RA,RB |
217 | 010 | mins RT,RA,RB |
218 | 011 | maxs RT,RA,RB |
219 | 100 | minuw RT,RA,RB |
220 | 101 | maxuw RT,RA,RB |
221 | 110 | minsw RT,RA,RB |
222 | 111 | maxsw RT,RA,RB |
229 |0 |6 |11 |16 |21 |31 |
230 | PO | RT | RA | RB | XO | Rc |
244 Special Registers altered:
250 Compute the unsigned minimum of RA and RB and store the result in RT.
262 |0 |6 |11 |16 |21 |31 |
263 | PO | RT | RA | RB | XO | Rc |
273 Special Registers altered:
279 Compute the unsigned maximum of RA and RB and store the result in RT.
293 |0 |6 |11 |16 |21 |31 |
294 | PO | RT | RA | RB | XO | Rc |
304 Special Registers altered:
309 Compute the signed minimum of RA and RB and store the result in RT.
321 |0 |6 |11 |16 |21 |31 |
322 | PO | RT | RA | RB | XO | Rc |
332 Compute the signed maximum of RA and RB and store the result in RT.
334 Special Registers altered:
344 # Instruction Formats
346 Add the following entries to Book I 1.6.1.15 X-FORM:
349 |0 |6 |11 |16 |21 |26 |31 |
350 | PO | FRT | FRA | FRB | FMM[0:3] / | XO | Rc |
353 Add a new field to Book I 1.6.2 Word Instruction Fields:
357 Field used to specify minimum/maximum mode for fminmax[s].
368 Appendix E Power ISA sorted by opcode
369 Appendix F Power ISA sorted by version
370 Appendix G Power ISA sorted by Compliancy Subset
371 Appendix H Power ISA sorted by mnemonic
373 | Form | Book | Page | Version | mnemonic | Description |
374 |------|------|------|---------|----------|-------------|
375 | A | I | # | 3.2B | fminmax | Floating Minimum/Maximum |
376 | A | I | # | 3.2B | fminmaxs | Floating Minimum/Maximum Single |
377 | ??? | I | # | 3.2B | minmax | Minimum/max Signed/Unsigned |
379 ## fmax instruction count
381 32 instructions are required in SFFS to emulate fmac.
382 <https://gcc.godbolt.org/z/6xba61To6>
386 fmax(double, double):
424 .byte 0,9,0,0,0,0,0,0