openpower/sv/setvl.mdwn

   1 # OpenPOWER SV setvl/setvli
   2
   3 See links:
   4
   5 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
   6 * <https://bugs.libre-soc.org/show_bug.cgi?id=535>
   7 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
   8
   9 # Format
  10
  11 | 0..5 |6..10|11..15|16.20|21.22.23.24..25|26.....30|31|  name   |
  12 |------|-----|------|-----|---------------|---------|--|---------|
  13 | 19   | RT  | RA   |     | XO[0:4]       | XO[5:9] |Rc| XL-Form |
  14 | 19   | RT  | RA   |imm  | imm //  vs ms | NNNNNN  |Rc| setvl/i |
  15
  16 # Pseudocode
  17
  18     // instruction fields:
  19     rd = get_rt_field();         // bits 6..10
  20     ra = get_ra_field();         // bits 11..15
  21     vlimmed = get_immed_field(); // bits 16..22
  22     vs = get_vs_field();         // bit 24
  23     ms = get_ms_field();         // bit 25
  24     Rc = get_Rc_field();         // bit 31
  25
  26     // set VL (or not).
  27     // 3 options: from SPR, from immed, from ra
  28     if vs {
  29        if ra == 0 {
  30            VL = SPR[SV_VL]
  31        } else {
  32            VL = vlimmed
  33        }
  34     } elif ra != 0 {
  35        VL = GPR[ra]
  36     }
  37
  38     // set MVL (or not).
  39     // 2 options: from SPR, from immed
  40     if ms {
  41        MVL = vlimmed
  42     } else {
  43        MVL = SPR[SV_MVL]
  44     }
  45
  46     // calculate (limit) VL
  47     VL = min(VL, MVL)
  48
  49     // store VL, MVL
  50     SPR[SV_VL] = VL
  51     SPR[SV_MVL] = MVL
  52
  53     // write rd
  54     if rt != 0 {
  55         // rt is not zero
  56         regs[rt] = VL;
  57         if Rc {
  58             // update CR from VL
  59         }
  60     }