openpower/sv/sif.py

   1 def sif(RA, mask=None, zero=False):
   2     RT = RA if mask is not None and not zero else 0
   3     i = 0
   4     # start setting if no predicate or if 1st predicate bit set
   5     setting_mode = mask is None
   6     while i < 16:
   7         bit = 1<<i
   8         if not setting_mode and mask is not None and (mask & bit):
   9             setting_mode = True # back into "setting" mode
  10         if setting_mode and mask is not None and not (mask & bit):
  11             setting_mode = False # masked out, stop setting
  12         if setting_mode:
  13             RT |= bit    # inclusively set bit in RT
  14             if RA & bit: # found a bit in rs1: stop setting RT
  15                 setting_mode = False
  16         i += 1
  17     return RT
  18
  19 if __name__ == '__main__':
  20      m  = 0b11000011
  21      v3 = 0b10010100 # vmsif.m v2, v3
  22      v2 = 0b11000011 # v2
  23      RT = sif(v3, m, zero=True)
  24      print(bin(v3), bin(v2), bin(RT))
  25      v3 = 0b10010100 # vmsif.m v2, v3
  26      v2 = 0b00000111 # v2 contents
  27      RT = sif(v3)
  28      print(bin(v3), bin(v2), bin(RT))
  29      v3 = 0b10010101 # vmsif.m v2, v3
  30      v2 = 0b00000001 # v2
  31      RT = sif(v3)
  32      print(bin(v3), bin(v2), bin(RT))
  33      v3 = 0b00000000 # vmsif.m v2, v3
  34      v2 = 0b11111111 # v2
  35      RT = sif(v3)
  36      print(bin(v3), bin(v2), bin(RT))