openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 There are five SPRs, available in any privilege level:
   6
   7 * MVL (the Maximum Vector Length)
   8 * VL (which has different characteristics from standard SPRs)
   9 * SUBVL (effectively a kind of SIMD)
  10 * STATE (containing copies of MVL, VL and SUBVL as well as context information)
  11
  12 For Privilege Levels (trap handling) there are the following SPRs,
  13 where x may be u, s or h for User, Supervisor or Hypervisor
  14 Modes respectively:
  15
  16 * (x)eSTATE (useful for saving and restoring during context switch,
  17   and for providing fast transitions)
  18
  19 The u/s SPRs are treated and handled exactly like their (x)epc
  20 equivalents.  On entry to or exit from a privilege level, the contents
  21 of its (x)eSTATE are swapped with STATE.
  22
  23 ## MAXVECTORLENGTH (MVL) <a name="mvl" />
  24
  25 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  26 is variable length and may be dynamically set.  MVL is
  27 however limited to the regfile bitwidth XLEN (1-32 for RV32,
  28 1-64 for RV64 and so on).
  29
  30 ## Vector Length (VL) <a name="vl" />
  31
  32 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  33 the range 1 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  34
  35     VL = rd = MIN(vlen, MVL)
  36
  37 where 1 <= MVL <= XLEN
  38
  39 ## SUBVL - Sub Vector Length
  40
  41 This is a "group by quantity" that effectively asks each iteration
  42 of the hardware loop to load SUBVL elements of width elwidth at a
  43 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  44 operation issued, SUBVL operations are issued.
  45
  46 The main effect of SUBVL is that predication bits are applied per
  47 **group**, rather than by individual element.  Legal values are 1 to 4.
  48 Illegal values raise an exception.
  49
  50 ## STATE
  51
  52 This is a standard SPR that contains sufficient information for a
  53 full context save/restore.  It contains (and permits setting of):
  54
  55 * MVL
  56 * VL
  57 * dsttoffs - the destination element offset of the current parallel
  58   instruction being executed
  59 * srcoffs - for twin-predication, the source element offset as well.
  60 * SUBVL
  61 * svoffs - the subvector element offset of the current
  62   parallel instruction being executed
  63
  64 The format of the STATE SPR is as follows:
  65
  66 | Field | Name     | Description           |
  67 | ----- | -------- | --------------------- |
  68 | 0:6   | maxvl    | Max Vector Length |
  69 | 7:13  |    vl    | Vector Length |
  70 | 14:20 | srcoffs  | |
  71 | 21:27 | dstoffs  | |
  72 | 28:29 | subvl    | |
  73 | 30:31 | svoffs   | |
  74
  75 The relationship between SUBVL and the subvl field is:
  76
  77 | SUBVL | (25..24) |
  78 | ----- | -------- |
  79 | 1     | 0b00     |
  80 | 2     | 0b01     |
  81 | 3     | 0b10     |
  82 | 4     | 0b11     |
  83
  84 Notes:
  85
  86 * The entries are truncated to be within range.  Attempts to set VL to
  87   greater than MAXVL will truncate VL.
  88 * Setting srcoffs, dstoffs to 64 or greater, or VL or MVL to greater than 64 is reserved and will cause an illegal instruction trap.
  89