openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 Note OpenPOWER v3.1 p12:
   6
   7      The designated SPR sandbox consists of non-privileged SPRs
   8      704-719 and privileged SPRs 720-735.
   9
  10 There are five SPRs, available in any privilege level:
  11
  12 * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
  13 * SVSRR0 which is used for exceptions and traps to store SVSTATE.
  14 * SVLR, a mirror of LR, used by Vectorised Branch
  15 * SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops
  16 * SVREMAP for applying specific shapes to specific registers
  17
  18 For Privilege Levels (trap handling) there are the following SPRs,
  19 where x may be u, s or h for User, Supervisor or Hypervisor
  20 Modes respectively:
  21
  22 * (x)eSTATE (useful for saving and restoring during context switch,
  23   and for providing fast transitions)
  24
  25 The u/s SPRs are treated and handled exactly like their (x)epc
  26 equivalents.  On entry to or exit from a privilege level, the contents
  27 of its (x)eSTATE are swapped with SVSTATE.
  28
  29 # SVSTATE
  30
  31 This is a standard SPR that contains sufficient information for a
  32 full context save/restore (see SVSRR0).  It contains (and permits setting of):
  33
  34 * MVL (the Maximum Vector Length) - declares (statically) how
  35   much of a regfile is to be reserved for Vector elements
  36 * VL - Vector Length
  37 * dststep - the destination element offset of the current parallel
  38   instruction being executed
  39 * srcstep - for twin-predication, the source element offset as well.
  40 * SUBVL
  41 * svstep - the subvector element offset of the current
  42   parallel instruction being executed
  43 * vfirst - Vertical First mode.  srcstep, dststep and substep
  44     **do not advance** unless explicitly requested to do so with
  45     pseudo-op svstep (a mode of setvl)
  46 * RMpst - REMAP persistence.  REMAP will apply only to the following
  47   instruction unless this bit is set, in which case REMAP "persists".
  48   Reset (cleared) on use of the `setvl` instruction if used to
  49   alter VL or MVL.
  50 * hphint - Horizontal Parallelism Hint. In Vertical First Mode
  51    hardware **MAY** perform up to this many elements in parallel
  52    per instruction. Set to zero to indicate "no hint".
  53 * SVme - REMAP enable bits, indicating which register is to be
  54  REMAPed.  RA, RB, RC, RT or EA.
  55 * mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
  56   indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
  57   should use.
  58
  59 **MAXVECTORLENGTH (MVL)** <a name="mvl" />
  60
  61 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  62 is variable length and may be dynamically set.  MVL is
  63 however limited to the regfile bitwidth, 64.
  64
  65 **Vector Length (VL)** <a name="vl" />
  66
  67 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  68 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  69
  70     VL = rd = MIN(vlen, MVL)
  71
  72 where 1 <= MVL <= XLEN
  73
  74 **SUBVL - Sub Vector Length**
  75
  76 This is a "group by quantity" that effectively asks each iteration
  77 of the hardware loop to load SUBVL elements of width elwidth at a
  78 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  79 operation issued, SUBVL operations are issued.
  80
  81 The main effect of SUBVL is that predication bits are applied per
  82 **group**, rather than by individual element.  Legal values are 1 to 4.
  83 Illegal values raise an exception.
  84
  85 For hphint, the number chosen must be consistently
  86 executed **every time**. Hardware is not permitted to execute five
  87 computations for one instruction then three on the next.
  88 hphint is a hint from the compiler to hardware that up to this
  89 many elements may be safely executed in parallel.
  90 Interestingly, when hphint is set equal to VL, it is in effect
  91 as if Vertical First mode were not set, because the hardware is
  92 given the option to run through all elements in an instruction.
  93 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
  94 except that the hardware may *choose* the number of elements.
  95
  96 *Note to programmers: changing VL during the middle of such modes
  97 should be done only with due care and respect for the fact that SVSTATE
  98 has exactly the same peer-level status as a Program Counter.*
  99
 100 The format of the SVSTATE SPR is as follows:
 101
 102 | Field | Name     | Description           |
 103 | ----- | -------- | --------------------- |
 104 | 0:6   | maxvl    | Max Vector Length     |
 105 | 7:13  |    vl    | Vector Length         |
 106 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
 107 | 21:27 | dststep  | for dststep = 0..VL-1 |
 108 | 28:29 | subvl    | Sub-vector length     |
 109 | 30:31 | svstep   | for svstep = 0..SUBVL-1  |
 110 | 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
 111 | 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
 112 | 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
 113 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 114 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 115 | 42:46 | SVme     | REMAP enable (RA-RT)  |
 116 | 47:48 | srcsubvl | Source Sub-vector length   |
 117 | 49:61 | rsvd     | reserved              |
 118 | 62    | RMpst    | REMAP persistence     |
 119 | 63    | vfirst   | Vertical First mode   |
 120
 121 The relationship between SUBVL and the subvl field is:
 122
 123 | SUBVL | (29..28) |
 124 | ----- | -------- |
 125 | 1     | 0b00     |
 126 | 2     | 0b01     |
 127 | 3     | 0b10     |
 128 | 4     | 0b11     |
 129
 130 Notes:
 131
 132 * The entries are truncated to be within range.  Attempts to set VL to
 133   greater than MAXVL will truncate VL.
 134 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
 135   than 64 is reserved and will cause an illegal instruction trap.
 136
 137 # SVSRR0
 138
 139 In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:
 140
 141 * SRR0 to store the PC (CIA/NIA)
 142 * SRR1 to store a copy of the MSR
 143
 144 Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way.  At any time PC is saved or restored, so is SVSTATE in **exactly** the same way for **exactly** the same reasons.  Thus, at an exception point,
 145 hardware **must** save/restore SVSTATE in SVSRR0 at exactly the same
 146 time that SRR0 is saved/restored in PC and SRR1 in MSR.
 147
 148 The SPR name given for the purposes of saving/restoring
 149 SVSTATE is SVSRR0.
 150
 151 # SVLR
 152
 153 SV Link Register, exactly analogous to LR (Link Register) may
 154 be used for temporary storage of SVSTATE, and, in particular,
 155 Vectorised Branch-Conditional instructions may interchange
 156 SVLR and SVSTATE whenever LR and NIA are.
 157
 158 Note that there is no equivalent Link variant of SVREMAP or
 159 SVSHAPE0-3, so SVLR has limited applicability