openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 There are five SPRs, available in any privilege level:
   6
   7 * MVL (the Maximum Vector Length)
   8 * VL (which has different characteristics from standard SPRs)
   9 * SUBVL (effectively a kind of SIMD)
  10 * STATE (containing copies of MVL, VL and SUBVL as well as context information)
  11 * SVSRR0 which is used for exceptions and traps to store SVSTATE.
  12
  13 MVL, VL and SUBVL are only provided for convenience: normally [[sv/setvl]] would be used to obtain a copy of VL, for example.
  14
  15 For Privilege Levels (trap handling) there are the following SPRs,
  16 where x may be u, s or h for User, Supervisor or Hypervisor
  17 Modes respectively:
  18
  19 * (x)eSTATE (useful for saving and restoring during context switch,
  20   and for providing fast transitions)
  21
  22 The u/s SPRs are treated and handled exactly like their (x)epc
  23 equivalents.  On entry to or exit from a privilege level, the contents
  24 of its (x)eSTATE are swapped with STATE.
  25
  26 # MAXVECTORLENGTH (MVL) <a name="mvl" />
  27
  28 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  29 is variable length and may be dynamically set.  MVL is
  30 however limited to the regfile bitwidth, 64.
  31
  32 # Vector Length (VL) <a name="vl" />
  33
  34 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  35 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  36
  37     VL = rd = MIN(vlen, MVL)
  38
  39 where 1 <= MVL <= XLEN
  40
  41 # SUBVL - Sub Vector Length
  42
  43 This is a "group by quantity" that effectively asks each iteration
  44 of the hardware loop to load SUBVL elements of width elwidth at a
  45 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  46 operation issued, SUBVL operations are issued.
  47
  48 The main effect of SUBVL is that predication bits are applied per
  49 **group**, rather than by individual element.  Legal values are 1 to 4.
  50 Illegal values raise an exception.
  51
  52 # STATE
  53
  54 This is a standard SPR that contains sufficient information for a
  55 full context save/restore (see SVSRR0).  It contains (and permits setting of):
  56
  57 * MVL
  58 * VL
  59 * dststep - the destination element offset of the current parallel
  60   instruction being executed
  61 * srcstep - for twin-predication, the source element offset as well.
  62 * SUBVL
  63 * svstep - the subvector element offset of the current
  64   parallel instruction being executed
  65
  66 The format of the STATE SPR is as follows:
  67
  68 | Field | Name     | Description           |
  69 | ----- | -------- | --------------------- |
  70 | 0:6   | maxvl    | Max Vector Length     |
  71 | 7:13  |    vl    | Vector Length         |
  72 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
  73 | 21:27 | dststep  | for dststep = 0..VL-1 |
  74 | 28:29 | subvl    | Sub-vector length     |
  75 | 30:31 | svstep   | for svstep = 0..VL-1  |
  76
  77 The relationship between SUBVL and the subvl field is:
  78
  79 | SUBVL | (25..24) |
  80 | ----- | -------- |
  81 | 1     | 0b00     |
  82 | 2     | 0b01     |
  83 | 3     | 0b10     |
  84 | 4     | 0b11     |
  85
  86 Notes:
  87
  88 * The entries are truncated to be within range.  Attempts to set VL to
  89   greater than MAXVL will truncate VL.
  90 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
  91   than 64 is reserved and will cause an illegal instruction trap.
  92
  93 # SVSRR0
  94
  95 In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:
  96
  97 * SRR0 to store the PC (CIA/NIA)
  98 * SRR1 to store a copy of the MSR
  99
 100 Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way.  At any time PC is saved or restored, so is SVSTATE in **exactly** the same way for **exactly** the same reasons.
 101
 102 The SPR name given for the purposes of saving/restoring SVSTATE is SVSRR0.
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