openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 Note Power ISA v3.1 p12:
   6
   7      The designated SPR sandbox consists of non-privileged SPRs
   8      704-719 and privileged SPRs 720-735.
   9
  10 There are eight SPRs, available in any privilege level:
  11
  12 * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
  13 * SVSRR0 which is used for exceptions and traps to store SVSTATE.
  14 * SVLR, a mirror of LR, used by Vectorised Branch
  15 * SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops
  16 * SVREMAP for applying specific shapes to specific registers
  17
  18 If SVSTATE is all zeros then SV is disabled and the contents of the
  19 other SPRs SVSHAPE/SVREMAP are ignored.
  20
  21 For Privilege Levels (trap handling) there are the following SPRs,
  22 where x may be u, s or h for User, Supervisor or Hypervisor
  23 Modes respectively:
  24
  25 * (x)eSTATE (useful for saving and restoring during context switch,
  26   and for providing fast transitions)
  27
  28 The u/s SPRs are treated and handled exactly like their (x)epc
  29 equivalents.  On entry to or exit from a privilege level, the contents
  30 of its (x)eSTATE are swapped with SVSTATE.
  31
  32 # SVSTATE
  33
  34 This is a standard SPR that (REMAP aside) contains sufficient information for a
  35 full context save/restore (see SVSRR0).  It contains (and permits setting of):
  36
  37 * MVL (the Maximum Vector Length) - declares (statically) how
  38   much of a regfile is to be reserved for Vector elements
  39 * VL - Vector Length
  40 * dststep - the destination element offset of the current parallel
  41   instruction being executed
  42 * srcstep - for twin-predication, the source element offset as well.
  43 * ssubstep - the source subvector element offset of the current
  44   parallel instruction being executed
  45 * dsubstep - the destination subvector element offset of the current
  46   parallel instruction being executed
  47 * vfirst - Vertical First mode.  srcstep, dststep and substep
  48     **do not advance** unless explicitly requested to do so with
  49     pseudo-op svstep (a mode of setvl)
  50 * RMpst - REMAP persistence.  REMAP will apply only to the following
  51   instruction unless this bit is set, in which case REMAP "persists".
  52   Reset (cleared) on use of the `setvl` instruction if used to
  53   alter VL or MVL.
  54 * hphint - Horizontal Parallelism Hint. Indicates that
  55   no Hazards exist between these elements. In Vertical First Mode
  56    hardware **MUST** perform this many elements in parallel
  57    per instruction. Set to zero to indicate "no hint".
  58 * SVme - REMAP enable bits, indicating which register is to be
  59  REMAPed.  RA, RB, RC, RT or EA.
  60 * mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
  61   indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
  62   should use.
  63
  64 **MAXVECTORLENGTH (MVL)** <a name="mvl" />
  65
  66 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  67 is variable length and may be dynamically set.  MVL is
  68 however limited to the regfile bitwidth, 64.
  69
  70 **Vector Length (VL)** <a name="vl" />
  71
  72 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  73 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  74
  75     VL = rd = MIN(vlen, MVL)
  76
  77 where 1 <= MVL <= XLEN
  78
  79 **SUBVL - Sub Vector Length**
  80
  81 This is a "group by quantity" that effectively asks each iteration
  82 of the hardware loop to load SUBVL elements of width elwidth at a
  83 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  84 operation issued, SUBVL operations are issued.
  85
  86 The main effect of SUBVL is that predication bits are applied per
  87 **group**, rather than by individual element.  Legal values are 1 to 4.
  88 Illegal values raise an exception.
  89
  90 **Horizontal Parallelism**
  91
  92 A problem exists for hardware where it may not be able to detect
  93 that a programmer (or compiler) knows of opportunities for parallelism
  94 and lack of overlap between loops.
  95
  96 For hphint, the number chosen must be consistently
  97 executed **every time**. Hardware is not permitted to execute five
  98 computations for one instruction then three on the next.
  99 hphint is a hint from the compiler to hardware that exactly this
 100 many elements may be safely executed in parallel, without hazards
 101 (including Memory accesses).
 102 Interestingly, when hphint is set equal to VL, it is in effect
 103 as if Vertical First mode were not set, because the hardware is
 104 given the option to run through all elements in an instruction.
 105 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
 106 except that the hardware may *choose* the number of elements.
 107
 108 *Note to programmers: changing VL during the middle of such modes
 109 should be done only with due care and respect for the fact that SVSTATE
 110 has exactly the same peer-level status as a Program Counter.*
 111
 112 **SVSTATE SPR**
 113
 114 The format of the SVSTATE SPR is as follows:
 115
 116 | Field | Name     | Description           |
 117 | ----- | -------- | --------------------- |
 118 | 0:6   | maxvl    | Max Vector Length     |
 119 | 7:13  |    vl    | Vector Length         |
 120 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
 121 | 21:27 | dststep  | for dststep = 0..VL-1 |
 122 | 28:29 | dsubstep | for substep = 0..SUBVL-1  |
 123 | 30:31 | ssubstep | for substep = 0..SUBVL-1  |
 124 | 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
 125 | 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
 126 | 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
 127 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 128 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 129 | 42:46 | SVme     | REMAP enable (RA-RT)  |
 130 | 47:t4 | rsvd     | reserved              |
 131 | 55:61 | hphint   | Horizontal Hint       |
 132 | 62    | RMpst    | REMAP persistence     |
 133 | 63    | vfirst   | Vertical First mode   |
 134
 135 Notes:
 136
 137 * The entries are truncated to be within range.  Attempts to set VL to
 138   greater than MAXVL will truncate VL.
 139 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
 140   than 64 is reserved and will cause an illegal instruction trap.
 141
 142 # SVSRR0
 143
 144 In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:
 145
 146 * SRR0 to store the PC (CIA/NIA)
 147 * SRR1 to store a copy of the MSR
 148
 149 Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way.  At any time PC is saved or restored, so is SVSTATE in **exactly** the same way for **exactly** the same reasons.  Thus, at an exception point,
 150 hardware **must** save/restore SVSTATE in SVSRR0 at exactly the same
 151 time that SRR0 is saved/restored in PC and SRR1 in MSR.
 152
 153 The SPR name given for the purposes of saving/restoring
 154 SVSTATE is SVSRR0.
 155
 156 # SVLR
 157
 158 SV Link Register, exactly analogous to LR (Link Register) may
 159 be used for temporary storage of SVSTATE, and, in particular,
 160 Vectorised Branch-Conditional instructions may interchange
 161 SVLR and SVSTATE whenever LR and NIA are.
 162
 163 Note that there is no equivalent Link variant of SVREMAP or
 164 SVSHAPE0-3 (it would be too costly), so SVLR has limited applicability:
 165 REMAP SPRs must be saved and restored explicitly.