openpower/sv/sprs.mdwn

   1 [[!tag standards]]
   2
   3 # SPRs <a name="sprs"></a>
   4
   5 Note Power ISA v3.1 p12:
   6
   7      The designated SPR sandbox consists of non-privileged SPRs
   8      704-719 and privileged SPRs 720-735.
   9
  10 There are eight SPRs, available in any privilege level:
  11
  12 * SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
  13 * SVLR, a mirror of LR, used by Vectorised Branch
  14 * SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops
  15 * SVREMAP for applying specific shapes to specific registers
  16
  17 If SVSTATE is all zeros then SV is disabled and the contents of the
  18 other SPRs SVSHAPE/SVREMAP are ignored.
  19
  20 For Privilege Levels (trap handling) there are the following SPRs,
  21 where x may be u, s or h for User, Supervisor or Hypervisor
  22 Modes respectively:
  23
  24 * (x)eSTATE (useful for saving and restoring during context switch,
  25   and for providing fast transitions)
  26
  27 The u/s SPRs are treated and handled exactly like their (x)epc
  28 equivalents.  On entry to or exit from a privilege level, the contents
  29 of its (x)SVSRR0 are swapped with SVSTATE.
  30
  31 # SVSTATE
  32
  33 This is a standard SPR that (REMAP aside) contains sufficient information for a
  34 full context save/restore (see SVSRR0).  It contains (and permits setting of):
  35
  36 * MVL (the Maximum Vector Length) - declares (statically) how
  37   much of a regfile is to be reserved for Vector elements
  38 * VL - Vector Length
  39 * dststep - the destination element offset of the current parallel
  40   instruction being executed
  41 * srcstep - for twin-predication, the source element offset as well.
  42 * ssubstep - the source subvector element offset of the current
  43   parallel instruction being executed
  44 * dsubstep - the destination subvector element offset of the current
  45   parallel instruction being executed
  46 * vfirst - Vertical First mode.  srcstep, dststep and substep
  47     **do not advance** unless explicitly requested to do so with
  48     pseudo-op svstep (a mode of setvl)
  49 * RMpst - REMAP persistence.  REMAP will apply only to the following
  50   instruction unless this bit is set, in which case REMAP "persists".
  51   Reset (cleared) on use of the `setvl` instruction if used to
  52   alter VL or MVL.
  53 * Pack - if set then srcstep/substep VL/SUBVL loop-ordering is inverted.
  54 * UnPack - if set then dststep/substep VL/SUBVL loop-ordering is inverted.
  55 * hphint - Horizontal Parallelism Hint. Indicates that
  56   no Hazards exist between this number of sequentially-accessed
  57    elements (including after REMAP). In Vertical First Mode
  58    hardware **MUST** perform this many elements in parallel
  59    per instruction. Set to zero to indicate "no hint".
  60 * SVme - REMAP enable bits, indicating which register is to be
  61  REMAPed.  RA, RB, RC, RT or EA.
  62 * mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
  63   indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
  64   should use.
  65
  66 **MAXVECTORLENGTH (MVL)** <a name="mvl" />
  67
  68 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  69 is variable length and may be dynamically set.  MVL is
  70 however limited to the regfile bitwidth, 64.
  71
  72 **Vector Length (VL)** <a name="vl" />
  73
  74 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  75 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  76
  77     VL = rd = MIN(vlen, MVL)
  78
  79 where 1 <= MVL <= XLEN
  80
  81 **SUBVL - Sub Vector Length**
  82
  83 This is a "group by quantity" that effectively asks each iteration
  84 of the hardware loop to load SUBVL elements of width elwidth at a
  85 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  86 operation issued, SUBVL operations are issued.
  87
  88 The main effect of SUBVL is that predication bits are applied per
  89 **group**, rather than by individual element.  Legal values are 1 to 4.
  90 Illegal values raise an exception.
  91
  92 **Horizontal Parallelism**
  93
  94 A problem exists for hardware where it may not be able to detect
  95 that a programmer (or compiler) knows of opportunities for parallelism
  96 and lack of overlap between loops.
  97
  98 For hphint, the number chosen must be consistently
  99 executed **every time**. Hardware is not permitted to execute five
 100 computations for one instruction then three on the next.
 101 hphint is a hint from the compiler to hardware that exactly this
 102 many elements may be safely executed in parallel, without hazards
 103 (including Memory accesses).
 104 Interestingly, when hphint is set equal to VL, it is in effect
 105 as if Vertical First mode were not set, because the hardware is
 106 given the option to run through all elements in an instruction.
 107 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
 108 except that the hardware may *choose* the number of elements.
 109
 110 *Note to programmers: changing VL during the middle of such modes
 111 should be done only with due care and respect for the fact that SVSTATE
 112 has exactly the same peer-level status as a Program Counter.*
 113
 114 **SVSTATE SPR**
 115
 116 The format of the SVSTATE SPR is as follows:
 117
 118 | Field | Name     | Description           |
 119 | ----- | -------- | --------------------- |
 120 | 0:6   | maxvl    | Max Vector Length     |
 121 | 7:13  |    vl    | Vector Length         |
 122 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
 123 | 21:27 | dststep  | for dststep = 0..VL-1 |
 124 | 28:29 | dsubstep | for substep = 0..SUBVL-1  |
 125 | 30:31 | ssubstep | for substep = 0..SUBVL-1  |
 126 | 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
 127 | 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
 128 | 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
 129 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
 130 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
 131 | 42:46 | SVme     | REMAP enable (RA-RT)  |
 132 | 47:52 | rsvd     | reserved              |
 133 | 53    | pack     | PACK (srcstrp reorder)  |
 134 | 54    | unpack   | UNPACK (dststep order)  |
 135 | 55:61 | hphint   | Horizontal Hint       |
 136 | 62    | RMpst    | REMAP persistence     |
 137 | 63    | vfirst   | Vertical First mode   |
 138
 139 Notes:
 140
 141 * The entries are truncated to be within range.  Attempts to set VL to
 142   greater than MAXVL will truncate VL.
 143 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
 144   than 64 is reserved and will cause an illegal instruction trap.
 145
 146 # SVLR
 147
 148 SV Link Register, exactly analogous to LR (Link Register) may
 149 be used for temporary storage of SVSTATE, and, in particular,
 150 Vectorised Branch-Conditional instructions may interchange
 151 SVLR and SVSTATE whenever LR and NIA are.
 152
 153 Note that there is no equivalent Link variant of SVREMAP or
 154 SVSHAPE0-3 (it would be too costly), so SVLR has limited applicability:
 155 REMAP SPRs must be saved and restored explicitly.