openpower/sv/sprs.mdwn

   1 # CSRs <a name="csrs"></a>
   2
   3 There are five CSRs, available in any privilege level:
   4
   5 * MVL (the Maximum Vector Length)
   6 * VL (which has different characteristics from standard CSRs)
   7 * SUBVL (effectively a kind of SIMD)
   8 * STATE (containing copies of MVL, VL and SUBVL as well as context information)
   9
  10 For Privilege Levels (trap handling) there are the following CSRs,
  11 where x may be u, s or h for User, Supervisor or Hypervisor
  12 Modes respectively:
  13
  14 * (x)eSTATE (useful for saving and restoring during context switch,
  15   and for providing fast transitions)
  16
  17 The u/s CSRs are treated and handled exactly like their (x)epc
  18 equivalents.  On entry to or exit from a privilege level, the contents
  19 of its (x)eSTATE are swapped with STATE.
  20
  21 ## MAXVECTORLENGTH (MVL) <a name="mvl" />
  22
  23 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
  24 is variable length and may be dynamically set.  MVL is
  25 however limited to the regfile bitwidth XLEN (1-32 for RV32,
  26 1-64 for RV64 and so on).
  27
  28 ## Vector Length (VL) <a name="vl" />
  29
  30 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
  31 the range 1 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
  32
  33     VL = rd = MIN(vlen, MVL)
  34
  35 where 1 <= MVL <= XLEN
  36
  37 ## SUBVL - Sub Vector Length
  38
  39 This is a "group by quantity" that effectively asks each iteration
  40 of the hardware loop to load SUBVL elements of width elwidth at a
  41 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
  42 operation issued, SUBVL operations are issued.
  43
  44 The main effect of SUBVL is that predication bits are applied per
  45 **group**, rather than by individual element.  Legal values are 1 to 4.
  46 Illegal values raise an exception.
  47
  48 ## STATE
  49
  50 This is a standard CSR that contains sufficient information for a
  51 full context save/restore.  It contains (and permits setting of):
  52
  53 * MVL
  54 * VL
  55 * destoffs - the destination element offset of the current parallel
  56   instruction being executed
  57 * srcoffs - for twin-predication, the source element offset as well.
  58 * SUBVL
  59 * dsvoffs - the subvector destination element offset of the current
  60   parallel instruction being executed
  61
  62 The format of the STATE CSR is as follows:
  63
  64 | Field | Name     | Description           |
  65 | ----- | -------- | --------------------- |
  66 | 0:6   | maxvl    | |
  67 | 7:13  |    vl    | |
  68 | 14:20 | srcoffs  | |
  69 | 21:27 | dstoffs  | |
  70 | 28:29 | subvl    | |
  71 | 30:31 | dsvoffs  | |
  72
  73
  74 The relationship between SUBVL and the subvl field is:
  75
  76 | SUBVL | (25..24) |
  77 | ----- | -------- |
  78 | 1     | 0b00     |
  79 | 2     | 0b01     |
  80 | 3     | 0b10     |
  81 | 4     | 0b11     |
  82
  83 Notes:
  84
  85 * The entries are truncated to be within range.  Attempts to set VL to
  86   greater than MAXVL will truncate VL.
  87 * Both VL and MAXVL are stored offset by one.  0b000000 represents VL=1,
  88   0b000001 represents VL=2.  This allows the full range 1 to XLEN instead
  89   of 0 to only 63.