openpower/sv/sprs.mdwn

   1 # SPRs  <a name="sprs"></a>
   2
   3 ## SVSTATE SPR
   4
   5
   6 The format of the SVSTATE SPR is as follows:
   7
   8 | Field | Name     | Description           |
   9 | ----- | -------- | --------------------- |
  10 | 0:6   | maxvl    | Max Vector Length     |
  11 | 7:13  |    vl    | Vector Length         |
  12 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
  13 | 21:27 | dststep  | for dststep = 0..VL-1 |
  14 | 28:29 | dsubstep | for substep = 0..SUBVL-1  |
  15 | 30:31 | ssubstep | for substep = 0..SUBVL-1  |
  16 | 32:33 | mi0      | REMAP RA/FRA/BFA SVSHAPE0-3    |
  17 | 34:35 | mi1      | REMAP RB/FRB/BFB SVSHAPE0-3    |
  18 | 36:37 | mi2      | REMAP RC/FRT SVSHAPE0-3    |
  19 | 38:39 | mo0      | REMAP RT/FRT/BF SVSHAPE0-3    |
  20 | 40:41 | mo1      | REMAP EA/RS/FRS SVSHAPE0-3    |
  21 | 42:46 | SVme     | REMAP enable (RA-RT)  |
  22 | 47:52 | rsvd     | reserved              |
  23 | 53    | pack     | PACK (srcstrp reorder)  |
  24 | 54    | unpack   | UNPACK (dststep order)  |
  25 | 55:61 | hphint   | Horizontal Hint       |
  26 | 62    | RMpst    | REMAP persistence     |
  27 | 63    | vfirst   | Vertical First mode   |
  28
  29 Notes:
  30
  31 * The entries are truncated to be within range.  Attempts to set VL to
  32   greater than MAXVL will truncate VL.
  33 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
  34   than 64 is reserved and will cause an illegal instruction trap.
  35
  36 **SVSTATE Fields**
  37
  38 SVSTATE is a standard SPR that (if REMAP is not activated) contains sufficient
  39 self-contaned information for a full context save/restore.
  40 SVSTATE contains (and permits setting of):
  41
  42 * MVL (the Maximum Vector Length) - declares (statically) how
  43   much of a regfile is to be reserved for Vector elements
  44 * VL - Vector Length
  45 * dststep - the destination element offset of the current parallel
  46   instruction being executed
  47 * srcstep - for twin-predication, the source element offset as well.
  48 * ssubstep - the source subvector element offset of the current
  49   parallel instruction being executed
  50 * dsubstep - the destination subvector element offset of the current
  51   parallel instruction being executed
  52 * vfirst - Vertical First mode.  srcstep, dststep and substep
  53     **do not advance** unless explicitly requested to do so with svstep
  54 * RMpst - REMAP persistence.  REMAP will apply only to the following
  55   instruction unless this bit is set, in which case REMAP "persists".
  56   Reset (cleared) on use of the `setvl` instruction if used to
  57   alter VL or MVL.
  58 * Pack - if set then srcstep/ssubstep VL/SUBVL loop-ordering is inverted.
  59 * UnPack - if set then dststep/dsubstep VL/SUBVL loop-ordering is inverted.
  60 * hphint - Horizontal Parallelism Hint. Indicates that
  61   no Hazards exist between groups of elements in sequential multiples of this number
  62    (before REMAP).  By definition: elements for which `FLOOR(srcstep/hphint)` is
  63    equal *before REMAP* are in the same parallelism "group". In Vertical First Mode
  64    hardware **MUST ONLY** process elements in the same group, and must stop
  65    Horizontal Issue at the last element of a given group. Set to zero to indicate "no hint".
  66 * SVme - REMAP enable bits, indicating which register is to be
  67    REMAPed: RA, RB, RC, RT and EA are the canonical (typical) register names
  68    associated with each bit, with RA being the LSB and EA being the MSB.
  69    See table below for ordering. When `SVme` is zero (0b00000) REMAP
  70    is **fully disabled and inactive** regardless of the contents of
  71   `SVSTATE`, `mi0-mi2/mo0-mo1`, or the four `SVSHAPEn` SPRs
  72 * mi0-mi2/mo0-mo1 - when the corresponding SVme bit is enabled, these
  73   indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
  74   should use, as long as the register's corresponding SVme bit is set
  75
  76 Programmer's Note: the fact that REMAP is entirely dormant when `SVme` is zero
  77 allows establishment of REMAP context well in advance, followed by utilising `svremap`
  78 at a precise (or the very last) moment.  Some implementations may exploit this
  79 to cache (or take some time to prepare caches) in the background whilst other
  80 (unrelated) instructions are being executed. This is particularly important to
  81 bear in mind when using `svindex` which will require hardware to perform (and
  82 cache) additional GPR reads.
  83
  84 Programmer's Note: when REMAP is activated it becomes necessary on any
  85 context-switch (Interrupt or Function call) to detect (or know in advance)
  86 that REMAP is enabled and to additionally save/restore the four SVSHAPE
  87 SPRs, SVHAPE0-3.  Given that this is expected to be a rare occurrence it was
  88 deemed unreasonable to burden every context-switch or function call with
  89 mandatory save/restore of SVSHAPEs, and consequently it is a *callee*
  90 (and Trap Handler) responsibility.  Callees (and Trap Handlers) **MUST**
  91 avoid using all and any SVP64 instructions during the period where state
  92 could be adversely affected.  SVP64 purely relies on Scalar instructions,
  93 so Scalar instructions (except the SVP64 Management ones and mtspr and
  94 mfspr) are 100% guaranteed to have zero impact on SVP64 state.
  95
  96 **Max Vector Length (maxvl)** <a name="mvl" />
  97
  98 MAXVECTORLENGTH is the same concept as MVL in RISC-V RVV, except that it
  99 is variable length and may be dynamically set (normally from an immediate
 100 field only).  MVL is limited to 7 bits
 101 (in the first version of SVP64) and consequently the maximum number of
 102 elements is limited to between 0 and 127.
 103
 104 Programmer's Note: Except by directly using `mtspr` on SVSTATE, which may
 105 result in performance penalties on some hardware implementations, SVSTATE's `maxvl`
 106 field may only be set **statically** as an immediate, by the `setvl` instruction.
 107 It may **NOT** be set dynamically from a register.  Compiler writers and assembly
 108 programmers are expected to perform static register file analysis, subdivision,
 109 and allocation and only utilise `setvl`. Direct writing to SVSTATE in order to
 110 "bypass" this Note could, in less-advanced implementations, potentially cause stalling,
 111 particularly if SVP64 instructions are issued directly after the `mtspr` to SVSTATE.
 112
 113 **Vector Length (vl)** <a name="vl" />
 114
 115 The actual Vector length, the number of elements in a "Vector", `SVSTATE.vl` may be set
 116 entirely dynamically at runtime from a number of sources. `setvl` is the primary
 117 instruction for setting Vector Length.
 118 `setvl` is conceptually similar but different from the Cray, SX Aurora, and RISC-V RVV
 119 equivalent. Similar to RVV, VL is set to be within
 120 the range 0 <= VL <= MVL. Unlike RVV, VL is set **exactly** according to the following:
 121
 122     VL = (RT|0) = MIN(vlen, MVL)
 123
 124 where 0 <= MVL <= 127 and vlen may come from an immediate, `RA`, or from the `CTR` SPR,
 125 depending on options selected with the `setvl` instruction.
 126
 127 Programmer's Note: conceptual understanding of Cray-style Vectors is far beyond the scope
 128 of the Power ISA Technical Reference.  Guidance on the 50-year-old Cray Vector paradigm is
 129 best sought elsewhere: good studies include Academic Courses given on the 1970s
 130 Cray Supercomputers over at least the past three decades.
 131
 132 **SUBVL - Sub Vector Length**
 133
 134 This is a "group by quantity" that effectively asks each iteration
 135 of the hardware loop to load SUBVL elements of width elwidth at a
 136 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
 137 operation issued, SUBVL operations are issued.
 138
 139 The main effect of SUBVL is that predication bits are applied per
 140 **group**, rather than by individual element.  Legal values are 0 to 3,
 141 representing 1 operation (1 element) thru 4 operations (4 elements) respectively.
 142 Elements are best though of in the context of 3D, Audio and Video: two Left and Right
 143 Channel "elements" or four ARGB "elements", or three XYZ coordinate "elements".
 144
 145 `subvl` is again primarily set by the `setvl` instruction. Not to be confused
 146 with `hphint`.
 147
 148 Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
 149 See `svstep` instruction for how to set Pack and Unpack Modes.
 150
 151
 152 **Horizontal Parallelism**
 153
 154 A problem exists for hardware where it may not be able to detect
 155 that a programmer (or compiler) knows of opportunities for parallelism
 156 and lack of overlap between loops.
 157
 158 For hphint, the number chosen must be consistently
 159 executed **every time**. Hardware is not permitted to execute five
 160 computations for one instruction then three on the next.
 161 hphint is a hint from the compiler to hardware that exactly this
 162 many elements may be safely executed in parallel, without hazards
 163 (including Memory accesses).
 164 Interestingly, when hphint is set equal to VL, it is in effect
 165 as if Vertical First mode were not set, because the hardware is
 166 given the option to run through all elements in an instruction.
 167 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
 168 except that the hardware may *choose* the number of elements.
 169
 170 Elements are considered to be in the same source batch if they have
 171 the same `FLOOR(srcstep/hphint)`. Likewise in the same destination batch.
 172 Three key observations here:
 173
 174 1. predication is **not** involved here.  the number of actual elements
 175 involved is considered *before* predicate masks are applied.
 176 2. twin predication can result in srcstep and dststep being in different
 177 batches
 178 3. batch evaluation is done *before* REMAP, making Hazard elimination easier
 179    for Multi-Issue systems.
 180
 181 *Hardare architectural note: each element within the same group may be treated as
 182 100% independent from any other element within that group, and therefore
 183 neither Register Hazards nor Memory Hazards inter-element exist.  This makes
 184 implementation far easier on resources.*
 185
 186 `hphint` may legitimately be set greater than `MAXVL`. This indicates to Multi-Issue
 187 hardware that even though MAXVL is relatively small the batches are *still independent*
 188 and therefore if Multi-Issue hardware chooses to allocate several batches up to
 189 `MAXVL` in size they are still independent.  This helps greatly simplify Multi-Issue
 190 systems by significantly reducing Hazards.
 191
 192 ## SVLR
 193
 194 SV Link Register, exactly analogous to LR (Link Register) may
 195 be used for temporary storage of SVSTATE, and, in particular,
 196 Vectorised Branch-Conditional instructions may interchange
 197 SVLR and SVSTATE whenever LR and NIA are.
 198
 199 Note that there is no equivalent Link variant of SVREMAP or
 200 SVSHAPE0-3 (it would be too costly), so SVLR has limited applicability:
 201 REMAP SPRs must be saved and restored explicitly.
 202
 203 [[!tag standards]]
 204