5 # XER, SO and other global flags
7 Vector systems are expected to be high performance. This is achieved
8 through parallelism, which requires that elements in the vector be
9 independent. XER SO and other global "accumulation" flags (CR.OV) cause
10 Read-Write Hazards on single-bit global resources, having a significant
13 Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including in cmp instructions) . XER is
14 simply neither read nor written. This includes when `scalar identity behaviour` occurs. If precise OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used without an SV Prefix.
16 An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used.
18 Regarding XER.CA: this does not fit either: it was designed for a scalar ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given Vector element. This provides a means to perform large parallel batches of Vectorised carry-capable additions. crweird instructions can be used to transfer the CRs in and out of an integer, where bitmanipulation may be performed to analyse the carry bits (including carry lookahead propagation) before continuing with further parallel additions.
20 # v3.0B/v3.1B relevant instructions
22 SV is primarily designed for use as an efficient hybrid 3D GPU / VPU / CPU ISA.
24 As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternative uses. Additionally, Vectorisation of the VSX SIMD system likewise makes no sense whatsoever. SV *replaces* VSX and provides, at the very minimum, predication (which VSX was designed without). Thus all VSX Major Opcodes - all of them - are "unused" and must raise illegal instruction exceptions in SV Prefix Mode.
26 Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to have because they are not only provided by SV, the SV alternatives may be predicated as well, making them far better suited to use in function calls and context-switching.
28 Additionally, some v3.0/1 instructions simply make no sense at all in a Vector context: `twi` and `tdi` fall into this category, as do branch operations as well as `sc` and `scv`. Here there is simply no point trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions should be called instead.
30 Fortuitously this leaves several Major Opcodes free for use by SV to fit alternative future instructions. In a 3D context this means Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA. With such instructions being included as standard in other commercially-successful GPU ISAs it is likewise critical that a 3D GPU/VPU based on svp64 also have such instructions.
32 Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions, and their discussion and specification is out of scope for this document.
34 Note, again: this is *only* under svp64 prefixing. Standard v3.0B / v3.1B is *not* altered by svp64 in any way.
36 ## Major opcode map (v3.0B)
38 This table is taken from v3.0B.
39 Table 9: Primary Opcode Map (opcode bits 0:5)
41 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
42 000 | | | tdi | twi | EXT04 | | | mulli | 000
43 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
44 010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm | | rlwnm | 010
45 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
46 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
47 101 | lhz | lhzu | lha | lhau | sth | sthu | lmw | stmw | 101
48 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
49 111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111
50 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
54 This is the same table containing v3.0B Primary Opcodes except those that make mo sense in a Vectorisation Context have been removed. These removed POs can, *in the SV Vector Context only*, be assigned to alternative (Vectorised-only) instructions, including future extensions.
56 Note, again, to emphasise: outside of svp64 these opcodes **do not** change. When not prefixed with svp64 these opcodes **specifically** retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
58 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
59 000 | | | | | | | | mulli | 000
60 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
61 010 | | | | EXT19 | rlwimi| rlwinm | | rlwnm | 010
62 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
63 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
64 101 | lhz | lhzu | lha | lhau | sth | sthu | | | 101
65 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
66 111 | | | EXT58 | EXT59 | | EXT61 | | EXT63 | 111
67 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
71 This is a novel concept that allows predication to be applied to a single
72 source and a single dest register. The following types of traditional
73 Vector operations may be encoded with it, *without requiring explicit
76 * VSPLAT (a single scalar distributed across a vector)
77 * VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
78 * VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
79 * VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
80 * VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))
82 Those patterns (and more) may be applied to:
84 * mv (the usual way that V\* ISA operations are created)
85 * exts\* sign-extension
86 * rwlinm and other RS-RA shift operations (**note**: excluding
87 those that take RA as both a src and dest. These are not
88 1-src 1-dest, they are 2-src, 1-dest)
89 * LD and ST (treating AGEN as one source)
90 * FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
91 * Condition Register ops mfcr, mtcr and other similar
93 This is a huge list that creates extremely powerful combinations,
94 particularly given that one of the predicate options is `(1<<r3)`
96 Additional unusual capabilities of Twin Predication include a back-to-back
97 version of VCOMPRESS-VEXPAND which is effectively the ability to do
98 sequentially ordered multiple VINSERTs. The source predicate selects a
99 sequentially ordered subset of elements to be inserted; the destination predicate specifies the sequentially ordered recipient locations.
100 This is equivalent to
101 `llvm.masked.compressstore.*`
103 `llvm.masked.expandload.*`
105 # Rounding, clamp and saturate
109 To help ensure that audio quality is not compromised by overflow,
110 "saturation" is provided, as well as a way to detect when saturation
111 occurred if desired (Rc=1). When Rc=1 there will be a *vector* of CRs, one CR per
112 element in the result (Note: this is different from VSX which has a
113 single CR per block).
115 When N=0 the result is saturated to within the maximum range of an
116 unsigned value. For integer ops this will be 0 to 2^elwidth-1. Similar
117 logic applies to FP operations, with the result being saturated to
118 maximum rather than returning INF, and the minimum to +0.0
120 When N=1 the same occurs except that the result is saturated to the min
121 or max of a signed result, and for FP to the min and max value rather than returning +/- INF.
123 When Rc=1, the CR "overflow" bit is set on the CR associated with the
124 element, to indicate whether saturation occurred. Note that due to
125 the hugely detrimental effect it has on parallel processing, XER.SO is
126 **ignored** completely and is **not** brought into play here. The CR
127 overflow bit is therefore simply set to zero if saturation did not occur,
128 and to one if it did.
130 Note also that saturate on operations that produce a carry output are prohibited due to the conflicting use of the CR.so bit for storing if saturation occurred.
132 Post-analysis of the Vector of CRs to find out if any given element hit
133 saturation may be done using a mapreduced CR op (cror), or by using the
134 new crweird instruction, transferring the relevant CR bits to a scalar
135 integer and testing it for nonzero. see [[sv/cr_int_predication]]
137 Note that the operation takes place at the maximum bitwidth (max of src and dest elwidth) and that truncation occurs to the range of the dest elwidth.
141 1. limited to single predicated dual src operations (add RT, RA, RB).
142 triple source operations are prohibited (fma).
143 2. limited to operations that make sense. divide is excluded, as is
144 subtract (X - Y - Z produces different answers depending on the order)
145 and asymmetric CRops (crandc, crorc). sane operations:
146 multiply, min/max, add, logical bitwise OR, most other CR ops.
147 operations that do have the same source and dest register type are
148 also excluded (isel, cmp). operations involving carry or overflow
149 (XER.CA / OV) are also prohibited.
150 3. the destination is a vector but the result is stored, ultimately,
151 in the first nonzero predicated element. all other nonzero predicated
152 elements are undefined. *this includes the CR vector* when Rc=1
153 4. implementations may use any ordering and any algorithm to reduce
154 down to a single result. However it must be equivalent to a straight
155 application of mapreduce. The destination vector (except masked out
156 elements) may be used for storing any intermediate results. these may
157 be left in the vector (undefined).
158 5. CRM applies when Rc=1. When CRM is zero, the CR associated with
159 the result is regarded as a "some results met standard CR result
160 criteria". When CRM is one, this changes to "all results met standard
162 6. implementations MAY use destoffs as well as srcoffs (see [[sv/sprs]])
163 in order to store sufficient state to resume operation should an
164 interrupt occur. this is also why implementations are permitted to use
165 the destination vector to store intermediary computations
166 7. *Predication may be applied*. zeroing mode is not an option. masked-out
167 inputs are ignored; masked-out elements in the destination vector are
168 unaltered (not used for the purposes of intermediary storage); the
169 scalar result is placed in the first available unmasked element.
171 Pseudocode for the case where RA==RB:
173 result = op(iregs[RA], iregs[RA+1])
175 for i in range(2, VL):
176 result = op(result, iregs[RA+i])
177 CRnew = analyse(result)
180 CR = CR bitwise or CRnew
182 CR = CR bitwise AND CRnew
184 TODO: case where RA!=RB which involves first a vector of 2-operand
185 results followed by a mapreduce on the intermediates.
187 Note that when SVM is clear and SUBVL!=1 the sub-elements are *independent*, i.e. they
188 are mapreduced per *sub-element* as a result. illustration with a vec2:
190 result.x = op(iregs[RA].x, iregs[RA+1].x)
191 result.y = op(iregs[RA].y, iregs[RA+1].y)
192 for i in range(2, VL):
193 result.x = op(result.x, iregs[RA+i].x)
194 result.y = op(result.y, iregs[RA+i].y)
196 Note here that Rc=1 does not make sense when SVM is clear and SUBVL!=1.
198 When SVM is set and SUBVL!=1, another variant is enabled: horizontal subvector mode. Example for a vec3:
201 result = op(iregs[RA+i].x, iregs[RA+i].x)
202 result = op(result, iregs[RA+i].y)
203 result = op(result, iregs[RA+i].z)
206 In this mode, when Rc=1 the Vector of CRs is as normal: each result element creates a corresponding CR element.
210 Data-dependent fail-on-first has two distinct variants: one for LD/ST,
211 the other for arithmetic operations (actually, CR-driven). Note in each
212 case the assumption is that vector elements are required appear to be
213 executed in sequential Program Order, element 0 being the first.
215 * LD/ST ffirst treats the first LD/ST in a vector (element 0) as an
216 ordinary one. Exceptions occur "as normal". However for elements 1
217 and above, if an exception would occur, then VL is **truncated** to the
219 * Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
220 CR-creating operation produces a result (including cmp). Similar to
221 branch, an analysis of the CR is performed and if the test fails, the
222 vector operation terminates and discards all element operations at and
223 above the current one, and VL is truncated to the *previous* element.
224 Thus the new VL comprises a contiguous vector of results, all of which
225 pass the testing criteria (equal to zero, less than zero).
227 The CR-based data-driven fail-on-first is new and not found in ARM SVE
228 or RVV. It is extremely useful for reducing instruction count, however
229 requires speculative execution involving modifications of VL to get high
230 performance implementations. An additional mode (RC1=1) effectively turns what would otherwise be an arithmetic operation into a type of `cmp`. The CR is stored (and the CR.eq bit tested). If the CR.eq bit fails then the Vector is truncated and the loop ends. Note that when RC1=1 the result elements arw never stored, only the CRs.
232 In CR-based data-driven fail-on-first there is only the option to select
233 and test one bit of each CR (just as with branch BO). For more complex
234 tests this may be insufficient. If that is the case, a vectorised crops
235 (crand, cror) may be used, and ffirst applied to the crop instead of to
236 the arithmetic vector.
238 One extremely important aspect of ffirst is:
240 * LDST ffirst may never set VL equal to zero. This because on the first
241 element an exception must be raised "as normal".
242 * CR-based data-dependent ffirst on the other hand **can** set VL equal
243 to zero. This is the only means in the entirety of SV that VL may be set
244 to zero (with the exception of via the SV.STATE SPR). When VL is set
245 zero due to the first element failing the CR bit-test, all subsequent
246 vectorised operations are effectively `nops` which is
247 *precisely the desired and intended behaviour*.
249 Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary. Likewise, to reduce workloads or balance resources.
251 CR-based data-dependent first on the other hand MUST not truncate VL arbitrarily. This because it is a precise test on which algorithms will rely.
255 This mode merges common CR testing with predication, saving on instruction count. Below is the pseudocode excluding predicate zeroing and elwidth overrides.
258 # predication test, skip all masked out elements.
259 if predicate_masked_out(i):
261 result = op(iregs[RA+i], iregs[RB+i])
262 CRnew = analyse(result) # calculates eq/lt/gt
263 # Rc=1 always stores the CR
265 crregs[offs+i] = CRnew
266 # now test CR, similar to branch
267 if RC1 or CRnew[BO[0:1]] != BO[2]:
268 continue # test failed: cancel store
269 # result optionally stored but CR always is
272 The reason for allowing the CR element to be stored is so that post-analysis
273 of the CR Vector may be carried out. For example: Saturation may have occurred (and been prevented from updating, by the test) but it is desirable to know *which* elements fail saturation.
275 Note that RC1 Mode basically turns all operations into `cmp`. The calculation is performed but it is only the CR that is written. The element result is *always* discarded, never written (just like `cmp`).
277 Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd.
279 ## pred-result mode on CR ops
281 Yes, really: CR operations (mtcr, crand, cror) may be Vectorised, predicated, and also pred-result mode applied to it. In this case, the Vectorisation applies to the batch of 4 bits, i.e. it is not the CR individual bits that are treated as the Vector, but the CRs themselves (CR0, CR8, CR9...)
283 Thus after each Vectorised operation (crand) a test of the CR result can in fact be performed.
287 CRs are slightly more involved than INT or FP registers due to the
288 possibility for indexing individual bits (crops BA/BB/BT). Again however
289 the access pattern needs to be understandable in relation to v3.0B / v3.1B
290 numbering, with a clear linear relationship and mapping existing when
293 ## CR EXTRA mapping table and algorithm
295 Numbering relationships for CR fields are already complex due to being
296 in BE format (*the relationship is not clearly explained in the v3.0B
297 or v3.1B specification*). However with some care and consideration
298 the exact same mapping used for INT and FP regfiles may be applied,
299 just to the upper bits, as explained below.
301 In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (2:4)
302 select one of the 8 CRs; the bottom 2 bits (0:1) select one of 4 bits
303 *in* that CR. The numbering was determined (after 4 months of
304 analysis and research) to be as follows:
306 CR_index = 7-(BA>>2) # top 3 bits but BE
307 bit_index = 3-(BA & 0b11) # low 2 bits but BE
308 CR_reg = CR[CR_index] # get the CR
309 # finally get the bit from the CR.
310 CR_bit = (CR_reg & (1<<bit_index)) != 0
312 When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
313 applies, **not** the CR\_bit portion (bits 0:1):
318 spec = EXTRA2<<1 | 0b0
320 # vector constructs "BA[2:4] spec[0:1] 0 BA[0:1]"
321 return ((BA >> 2)<<5) | # hi 3 bits shifted up
322 (spec[0:1]<<3) | # to make room for these
323 (BA & 0b11) # CR_bit on the end
325 # scalar constructs "0 spec[0:1] BA[0:4]"
326 return (spec[0:1] << 5) | BA
328 Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
329 algorithm to determin CR\_reg is modified to as follows:
331 CR_index = 7-(BA>>2) # top 3 bits but BE
334 CR_index = (CR_index<<3) | (spec[0:1] << 1)
337 CR_index = (spec[0:1]<<3) | CR_index
338 # same as for v3.0/v3.1 from this point onwards
339 bit_index = 3-(BA & 0b11) # low 2 bits but BE
340 CR_reg = CR[CR_index] # get the CR
341 # finally get the bit from the CR.
342 CR_bit = (CR_reg & (1<<bit_index)) != 0
344 Note here that the decoding pattern to determine CR\_bit does not change.
346 Note: high-performance implementations may read/write Vectors of CRs in
347 batches of aligned 32-bit chunks (CR0-7, CR7-15). This is to greatly
348 simplify internal design. If instructions are issued where CR Vectors
349 do not start on a 32-bit aligned boundary, performance may be affected.
351 ## CR fields as inputs/outputs of vector operations
353 CRs (or, the arithmetic operations associated with them)
354 may be marked as Vectorised or Scalar. When Rc=1 in arithmetic operations that have no explicit EXTRA to cover the CR, the CR is Vectorised if the destination is Vectorised. Likewise if the destination is scalar then so is the CR.
356 When vectorized, the CR inputs/outputs are sequentially read/written
357 to 4-bit CR fields. Vectorised Integer results, when Rc=1, will begin
358 writing to CR8 (TBD evaluate) and increase sequentially from there.
361 * implementations may rely on the Vector CRs being aligned to 8. This
362 means that CRs may be read or written in aligned batches of 32 bits
363 (8 CRs per batch), for high performance implementations.
364 * scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not
365 overwritten by vector Rc=1 operations except for very large VL
366 * CR-based predication, from CR32, is also not interfered with
367 (except by large VL).
369 However when the SV result (destination) is marked as a scalar by the
370 EXTRA field the *standard* v3.0B behaviour applies: the accompanying
371 CR when Rc=1 is written to. This is CR0 for integer operations and CR1
374 Note that yes, the CRs are genuinely Vectorised. Unlike in SIMD VSX which
375 has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
376 v3.0B scalar operations produce a **tuple** of element results: the
377 result of the operation as one part of that element *and a corresponding
378 CR element*. Greatly simplified pseudocode:
381 # calculate the vector result of an add
382 iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
383 # now calculate CR bits
384 CRs[8+i].eq = iregs[RT+i] == 0
385 CRs[8+i].gt = iregs[RT+i] > 0
388 If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
389 then a followup instruction must be performed, setting "reduce" mode on
390 the Vector of CRs, using cr ops (crand, crnor)to do so. This provides far
391 more flexibility in analysing vectors than standard Vector ISAs. Normal
392 Vector ISAs are typically restricted to "were all results nonzero" and
393 "were some results nonzero". The application of mapreduce to Vectorised
394 cr operations allows far more sophisticated analysis, particularly in
395 conjunction with the new crweird operations see [[sv/cr_int_predication]].
397 Note in particular that the use of a separate instruction in this way
398 ensures that high performance multi-issue OoO inplementations do not
399 have the computation of the cumulative analysis CR as a bottleneck and
400 hindrance, regardless of the length of VL.
402 (see [[discussion]]. some alternative schemes are described there)
404 ## Rc=1 when SUBVL!=1
406 sub-vectors are effectively a form of SIMD (length 2 to 4). Only 1 bit of predicate is allocated per subvector; likewise only one CR is allocated
409 This leaves a conundrum as to how to apply CR computation per subvector, when normally Rc=1 is exclusively applied to scalar elements. A solution is to perform a bitwise OR or AND of the subvector tests. Given that OE is ignored, rhis field may (when available) be used to select OR or AND behavior.
411 ### Table of CR fields
413 CR[i] is the notation used by the OpenPower spec to refer to CR field #i,
414 so FP instructions with Rc=1 write to CR[1] aka SVCR1_000.
416 CRs are not stored in SPRs: they are registers in their own right.
417 Therefore context-switching the full set of CRs involves a Vectorised
418 mfcr or mtcr, using VL=64, elwidth=8 to do so. This is exactly as how scalar OpenPOWER context-switches CRs: it is just that there are now more of them.
420 The 64 SV CRs are arranged similarly to the way the 128 integer registers
421 are arranged. TODO a python program that auto-generates a CSV file
422 which can be included in a table, which is in a new page (so as not to
423 overwhelm this one). [[svp64/cr_names]]
427 **NOTE THIS TABLE SHOULD NO LONGER BE HAND EDITED** see
428 <https://bugs.libre-soc.org/show_bug.cgi?id=548> for details.
430 Instructions are broken down by Register Profiles as listed in the
431 following auto-generated page: [[opcode_regs_deduped]]. "Non-SV"
432 indicates that the operations with this Register Profile cannot be
433 Vectorised (mtspr, bc, dcbz, twi)
435 TODO generate table which will be here [[svp64/reg_profiles]]
437 # SV pseudocode illilustration
439 ## Single-predicated Instruction
441 illustration of normal mode add operation: zeroing not included, elwidth overrides not included. if there is no predicate, it is set to all 1s
443 function op_add(rd, rs1, rs2) # add not VADD!
444 int i, id=0, irs1=0, irs2=0;
445 predval = get_pred_val(FALSE, rd);
446 for (i = 0; i < VL; i++)
447 STATE.srcoffs = i # save context
448 if (predval & 1<<i) # predication uses intregs
449 ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
450 if (!int_vec[rd ].isvec) break;
451 if (rd.isvec) { id += 1; }
452 if (rs1.isvec) { irs1 += 1; }
453 if (rs2.isvec) { irs2 += 1; }
454 if (id == VL or irs1 == VL or irs2 == VL) {
455 # end VL hardware loop
456 STATE.srcoffs = 0; # reset
460 This has several modes:
463 * RT.v = RA.v RB.s (and RA.s RB.v)
466 * RT.s = RA.v RB.s (and RA.s RB.v)
469 All of these may be predicated. Vector-Vector is straightfoward. When one of source is a Vector and the other a Scalar, it is clear that each element of the Vector source should be added to the Scalar source, each result placed into the Vector (or, if the destination is a scalar, only the first nonpredicated result).
471 The one that is not obvious is RT=vector but both RA/RB=scalar. Here this acts as a "splat scalar result", copying the same result into all nonpredicated result elements. If a fixed destination scalar was intended, then an all-Scalar operation should be used.
473 See <https://bugs.libre-soc.org/show_bug.cgi?id=552>
475 # Assembly Annotation
477 Assembly code annotation is required for SV to be able to successfully
478 mark instructions as "prefixed".
480 A reasonable (prototype) starting point:
486 * ew=8/16/32 - element width
487 * sew=8/16/32 - source element width
489 * mode=reduce/satu/sats/crpred
490 * pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
493 similar to x86 "rex" prefix.