5 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturation
6 * <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47> Parallel Prefix
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=697> Reduce Modes
8 * <https://bugs.libre-soc.org/show_bug.cgi?id=864> parallel prefix simulator
9 * <https://bugs.libre-soc.org/show_bug.cgi?id=809> OV sv.addex discussion
11 This is the appendix to [[sv/svp64]], providing explanations of modes
12 etc. leaving the main svp64 page's primary purpose as outlining the
19 # Partial Implementations
21 It is perfectly legal to implement subsets of SVP64 as long as illegal
22 instruction traps are always raised on unimplemented features,
23 so that soft-emulation is possible,
24 even for future revisions of SVP64. With SVP64 being partly controlled
25 through contextual SPRs, a little care has to be taken.
28 not implemented including reserved ones for future use must raise an illegal
29 instruction trap if read or written. This allows software the
30 opportunity to emulate the context created by the given SPR.
32 See [[sv/compliancy_levels]] for full details.
34 # XER, SO and other global flags
36 Vector systems are expected to be high performance. This is achieved
37 through parallelism, which requires that elements in the vector be
38 independent. XER SO/OV and other global "accumulation" flags (CR.SO) cause
39 Read-Write Hazards on single-bit global resources, having a significant
42 Consequently in SV, XER.SO behaviour is disregarded (including
43 in `cmp` instructions). XER.SO is not read, but XER.OV may be written,
44 breaking the Read-Modify-Write Hazard Chain that complicates
45 microarchitectural implementations.
46 This includes when `scalar identity behaviour` occurs. If precise
47 OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1
48 instructions should be used without an SV Prefix.
50 TODO jacob add about OV https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-large-integer-arithmetic-paper.pdf
52 Of note here is that XER.SO and OV may already be disregarded in the
53 Power ISA v3.0/1 SFFS (Scalar Fixed and Floating) Compliancy Subset.
54 SVP64 simply makes it mandatory to disregard XER.SO even for other Subsets,
55 but only for SVP64 Prefixed Operations.
57 XER.CA/CA32 on the other hand is expected and required to be implemented
58 according to standard Power ISA Scalar behaviour. Interestingly, due
59 to SVP64 being in effect a hardware for-loop around Scalar instructions
60 executing in precise Program Order, a little thought shows that a Vectorised
61 Carry-In-Out add is in effect a Big Integer Add, taking a single bit Carry In
62 and producing, at the end, a single bit Carry out. High performance
63 implementations may exploit this observation to deploy efficient
64 Parallel Carry Lookahead.
66 # assume VL=4, this results in 4 sequential ops (below)
67 sv.adde r0.v, r4.v, r8.v
69 # instructions that get executed in backend hardware:
70 adde r0, r4, r8 # takes carry-in, produces carry-out
71 adde r1, r5, r9 # takes carry from previous
73 adde r3, r7, r11 # likewise
75 It can clearly be seen that the carry chains from one
76 64 bit add to the next, the end result being that a
77 256-bit "Big Integer Add with Carry" has been performed, and that
78 CA contains the 257th bit. A one-instruction 512-bit Add-with-Carry
79 may be performed by setting VL=8, and a one-instruction
80 1024-bit Add-with-Carry by setting VL=16, and so on. More on
81 this in [[openpower/sv/biginteger]]
83 # v3.0B/v3.1 relevant instructions
85 SV is primarily designed for use as an efficient hybrid 3D GPU / VPU /
88 Vectorisation of the VSX Packed SIMD system makes no sense whatsoever,
89 the sole exceptions potentially being any operations with 128-bit
90 operands such as `vrlq` (Rotate Quad Word) and `xsaddqp` (Scalar
92 SV effectively *replaces* the majority of VSX, requiring far less
93 instructions, and provides, at the very minimum, predication
94 (which VSX was designed without).
96 Likewise, Load/Store Multiple make no sense to
97 have because they are not only provided by SV, the SV alternatives may
98 be predicated as well, making them far better suited to use in function
99 calls and context-switching.
101 Additionally, some v3.0/1 instructions simply make no sense at all in a
102 Vector context: `rfid` falls into this category,
103 as well as `sc` and `scv`. Here there is simply no point
104 trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions
105 should be called instead.
107 Fortuitously this leaves several Major Opcodes free for use by SV
108 to fit alternative future instructions. In a 3D context this means
109 Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST
110 operations, and others critical to an efficient, effective 3D GPU and
111 VPU ISA. With such instructions being included as standard in other
112 commercially-successful GPU ISAs it is likewise critical that a 3D
113 GPU/VPU based on svp64 also have such instructions.
115 Note however that svp64 is stand-alone and is in no way
116 critically dependent on the existence or provision of 3D GPU or VPU
117 instructions. These should be considered entirely separate
118 extensions, and their discussion
119 and specification is out of scope for this document.
121 ## Major opcode map (v3.0B)
123 This table is taken from v3.0B.
124 Table 9: Primary Opcode Map (opcode bits 0:5)
127 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
128 000 | | | tdi | twi | EXT04 | | | mulli | 000
129 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001
130 010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm | | rlwnm | 010
131 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011
132 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100
133 101 | lhz | lhzu | lha | lhau | sth | sthu | lmw | stmw | 101
134 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110
135 111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111
136 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
139 It is important to note that having a different v3.0B Scalar opcode
140 that is different from an SVP64 one is highly undesirable: the complexity
141 in the decoder is greatly increased, through breaking of the RISC paradigm.
143 # EXTRA Field Mapping
145 The purpose of the 9-bit EXTRA field mapping is to mark individual
146 registers (RT, RA, BFA) as either scalar or vector, and to extend
147 their numbering from 0..31 in Power ISA v3.0 to 0..127 in SVP64.
148 Three of the 9 bits may also be used up for a 2nd Predicate (Twin
149 Predication) leaving a mere 6 bits for qualifying registers. As can
150 be seen there is significant pressure on these (and in fact all) SVP64 bits.
152 In Power ISA v3.1 prefixing there are bits which describe and classify
153 the prefix in a fashion that is independent of the suffix. MLSS for
154 example. For SVP64 there is insufficient space to make the SVP64 Prefix
155 "self-describing", and consequently every single Scalar instruction
156 had to be individually analysed, by rote, to craft an EXTRA Field Mapping.
157 This process was semi-automated and is described in this section.
158 The final results, which are part of the SVP64 Specification, are here:
159 [[openpower/opcode_regs_deduped]]
161 * Firstly, every instruction's mnemonic (`add RT, RA, RB`) was analysed
162 from reading the markdown formatted version of the Scalar pseudocode
163 which is machine-readable and found in [[openpower/isatables]]. The
164 analysis gives, by instruction, a "Register Profile". `add RT, RA, RB`
165 for example is given a designation `RM-2R-1W` because it requires
166 two GPR reads and one GPR write.
167 * Secondly, the total number of registers was added up (2R-1W is 3 registers)
168 and if less than or equal to three then that instruction could be given an
169 EXTRA3 designation. Four or more is given an EXTRA2 designation because
170 there are only 9 bits available.
171 * Thirdly, the instruction was analysed to see if Twin or Single
172 Predication was suitable. As a general rule this was if there
173 was only a single operand and a single result (`extw` and LD/ST)
174 however it was found that some 2 or 3 operand instructions also
175 qualify. Given that 3 of the 9 bits of EXTRA had to be sacrificed for use
176 in Twin Predication, some compromises were made, here. LDST is
177 Twin but also has 3 operands in some operations, so only EXTRA2 can be used.
178 * Fourthly, a packing format was decided: for 2R-1W an EXTRA3 indexing
179 could have been decided
180 that RA would be indexed 0 (EXTRA bits 0-2), RB indexed 1 (EXTRA bits 3-5)
181 and RT indexed 2 (EXTRA bits 6-8). In some cases (LD/ST with update)
182 RA-as-a-source is given a **different** EXTRA index from RA-as-a-result
183 (because it is possible to do, and perceived to be useful). Rc=1
184 co-results (CR0, CR1) are always given the same EXTRA index as their
185 main result (RT, FRT).
186 * Fifthly, in an automated process the results of the analysis
187 were outputted in CSV Format for use in machine-readable form
188 by sv_analysis.py <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
190 This process was laborious but logical, and, crucially, once a
191 decision is made (and ratified) cannot be reversed.
192 Qualifying future Power ISA Scalar instructions for SVP64
193 is **strongly** advised to utilise this same process and the same
194 sv_analysis.py program as a canonical method of maintaining the
195 relationships. Alterations to that same program which
196 change the Designation is **prohibited** once finalised (ratified
197 through the Power ISA WG Process). It would
198 be similar to deciding that `add` should be changed from X-Form
201 # Single Predication <a name="1p"> </a>
203 This is a standard mode normally found in Vector ISAs. every element in every source Vector and in the destination uses the same bit of one single predicate mask.
205 In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep, but depending on whether sz and/or dz are set, srcstep and
206 dststep can still potentially become different indices. Only when sz=dz
207 is srcstep guaranteed to equal dststep at all times.
209 Note that in some Mode Formats there is only one flag (zz). This indicates
210 that *both* sz *and* dz are set to the same.
218 The following schedule for srcstep and dststep will occur:
220 | srcstep | dststep | comment |
221 | ---- | ----- | -------- |
222 | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 |
223 | 1 | 2 | sz=1 but dz=0: dst skips mask[1], src soes not |
224 | 2 | 3 | mask[src=2] and mask[dst=3] are 1 |
225 | end | end | loop has ended because dst reached VL-1 |
233 The following schedule for srcstep and dststep will occur:
235 | srcstep | dststep | comment |
236 | ---- | ----- | -------- |
237 | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 |
238 | 2 | 1 | sz=0 but dz=1: src skips mask[1], dst does not |
239 | 3 | 2 | mask[src=3] and mask[dst=2] are 1 |
240 | end | end | loop has ended because src reached VL-1 |
242 In both these examples it is crucial to note that despite there being
243 a single predicate mask, with sz and dz being different, srcstep and
244 dststep are being requested to react differently.
252 The following schedule for srcstep and dststep will occur:
254 | srcstep | dststep | comment |
255 | ---- | ----- | -------- |
256 | 0 | 0 | both mask[src=0] and mask[dst=0] are 1 |
257 | 2 | 2 | sz=0 and dz=0: both src and dst skip mask[1] |
258 | 3 | 3 | mask[src=3] and mask[dst=3] are 1 |
259 | end | end | loop has ended because src and dst reached VL-1 |
261 Here, both srcstep and dststep remain in lockstep because sz=dz=1
263 # Twin Predication <a name="2p"> </a>
265 This is a novel concept that allows predication to be applied to a single
266 source and a single dest register. The following types of traditional
267 Vector operations may be encoded with it, *without requiring explicit
270 * VSPLAT (a single scalar distributed across a vector)
271 * VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
272 * VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
273 * VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
274 * VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))
276 Those patterns (and more) may be applied to:
278 * mv (the usual way that V\* ISA operations are created)
279 * exts\* sign-extension
280 * rwlinm and other RS-RA shift operations (**note**: excluding
281 those that take RA as both a src and dest. These are not
282 1-src 1-dest, they are 2-src, 1-dest)
283 * LD and ST (treating AGEN as one source)
284 * FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc.
285 * Condition Register ops mfcr, mtcr and other similar
287 This is a huge list that creates extremely powerful combinations,
288 particularly given that one of the predicate options is `(1<<r3)`
290 Additional unusual capabilities of Twin Predication include a back-to-back
291 version of VCOMPRESS-VEXPAND which is effectively the ability to do
292 sequentially ordered multiple VINSERTs. The source predicate selects a
293 sequentially ordered subset of elements to be inserted; the destination
294 predicate specifies the sequentially ordered recipient locations.
295 This is equivalent to
296 `llvm.masked.compressstore.*`
298 `llvm.masked.expandload.*`
299 with a single instruction.
301 This extreme power and flexibility comes down to the fact that SVP64
302 is not actually a Vector ISA: it is a loop-abstraction-concept that
303 is applied *in general* to Scalar operations, just like the x86
304 `REP` instruction (if put on steroids).
306 # EXTRA Pack/Unpack Modes
308 The pack/unpack concept of VSX `vpack` is abstracted out as a Sub-Vector
309 reordering Schedule, named `RM-2P-1S1D-PU`.
310 The usual RM-2P-1S1D is reduced from EXTRA3 to EXTRA2, making
311 room for 2 extra bits that enable either "packing" or "unpacking"
312 on the subvectors vec2/3/4.
315 "normal" SVP64 operation with `SUBVL!=1:` (assuming no elwidth overrides):
319 for j in range(SUBVL):
325 For pack/unpack (again, no elwidth overrides):
327 # yield an outer-SUBVL or inner VL loop with SUBVL
330 for j in range(SUBVL):
335 for j in range(SUBVL):
338 # walk through both source and dest indices simultaneously
339 for src_idx, dst_idx in zip(index_p(PACK), index_p(UNPACK)):
340 move_operation(RT+dst_idx, RA+src_idx)
342 "yield" from python is used here for simplicity and clarity.
343 The two Finite State Machines for the generation of the source
344 and destination element offsets progress incrementally in
347 Example VL=2, SUBVL=3, PACK_en=1
359 Setting of both `PACK_en` and `UNPACK_en` is neither prohibited nor
360 `UNDEFINED` because the reordering is fully deterministic, and
361 additional REMAP reordering may be applied. For Matrix this would
362 give potentially up to 4 Dimensions of reordering.
364 Pack/Unpack applies to mv operations, mv.swizzle,
365 and some other single-source
366 single-destination operations such as Indexed LD/ST and extsw.
367 [[sv/mv.swizzle]] has a slightly different pseudocode algorithm
368 for Vertical-First Mode.
372 Reduction in SVP64 is deterministic and somewhat of a misnomer. A normal
373 Vector ISA would have explicit Reduce opcodes with defined characteristics
374 per operation: in SX Aurora there is even an additional scalar argument
375 containing the initial reduction value, and the default is either 0
376 or 1 depending on the specifics of the explicit opcode.
377 SVP64 fundamentally has to
378 utilise *existing* Scalar Power ISA v3.0B operations, which presents some
381 The solution turns out to be to simply define reduction as permitting
382 deterministic element-based schedules to be issued using the base Scalar
383 operations, and to rely on the underlying microarchitecture to resolve
384 Register Hazards at the element level. This goes back to
385 the fundamental principle that SV is nothing more than a Sub-Program-Counter
386 sitting between Decode and Issue phases.
388 For Scalar Reduction,
389 Microarchitectures *may* take opportunities to parallelise the reduction
390 but only if in doing so they preserve strict Program Order at the Element Level.
391 Opportunities where this is possible include an `OR` operation
392 or a MIN/MAX operation: it may be possible to parallelise the reduction,
393 but for Floating Point it is not permitted due to different results
394 being obtained if the reduction is not executed in strict Program-Sequential
397 In essence it becomes the programmer's responsibility to leverage the
398 pre-determined schedules to desired effect.
400 ## Scalar result reduction and iteration
402 Scalar Reduction per se does not exist, instead is implemented in SVP64
403 as a simple and natural relaxation of the usual restriction on the Vector
404 Looping which would terminate if the destination was marked as a Scalar.
405 Scalar Reduction by contrast *keeps issuing Vector Element Operations*
406 even though the destination register is marked as scalar.
407 Thus it is up to the programmer to be aware of this, observe some
408 conventions, and thus end up achieving the desired outcome of scalar
411 It is also important to appreciate that there is no
412 actual imposition or restriction on how this mode is utilised: there
413 will therefore be several valuable uses (including Vector Iteration
415 and it is up to the programmer to make best use of the
416 (strictly deterministic) capability
419 In this mode, which is suited to operations involving carry or overflow,
420 one register must be assigned, by convention by the programmer to be the
421 "accumulator". Scalar reduction is thus categorised by:
423 * One of the sources is a Vector
424 * the destination is a scalar
425 * optionally but most usefully when one source scalar register is
426 also the scalar destination (which may be informally termed
428 * That the source register type is the same as the destination register
429 type identified as the "accumulator". Scalar reduction on `cmp`,
430 `setb` or `isel` makes no sense for example because of the mixture
431 between CRs and GPRs.
433 *Note that issuing instructions in Scalar reduce mode such as `setb`
434 are neither `UNDEFINED` nor prohibited, despite them not making much
435 sense at first glance.
436 Scalar reduce is strictly defined behaviour, and the cost in
437 hardware terms of prohibition of seemingly non-sensical operations is too great.
438 Therefore it is permitted and required to be executed successfully.
439 Implementors **MAY** choose to optimise such instructions in instances
440 where their use results in "extraneous execution", i.e. where it is clear
441 that the sequence of operations, comprising multiple overwrites to
442 a scalar destination **without** cumulative, iterative, or reductive
443 behaviour (no "accumulator"), may discard all but the last element
444 operation. Identification
445 of such is trivial to do for `setb` and `cmp`: the source register type is
446 a completely different register file from the destination.
447 Likewise Scalar reduction when the destination is a Vector
448 is as if the Reduction Mode was not requested. However it would clearly
449 be unacceptable to perform such optimisations on cache-inhibited LD/ST,
450 so some considerable care needs to be taken.*
452 Typical applications include simple operations such as `ADD r3, r10.v,
453 r3` where, clearly, r3 is being used to accumulate the addition of all
454 elements of the vector starting at r10.
456 # add RT, RA,RB but when RT==RA
458 iregs[RA] += iregs[RB+i] # RT==RA
460 However, *unless* the operation is marked as "mapreduce" (`sv.add/mr`)
462 **terminates** at the first scalar operation. Only by marking the
463 operation as "mapreduce" will it continue to issue multiple sub-looped
464 (element) instructions in `Program Order`.
466 To perform the loop in reverse order, the ```RG``` (reverse gear) bit must be set. This may be useful in situations where the results may be different
467 (floating-point) if executed in a different order. Given that there is
468 no actual prohibition on Reduce Mode being applied when the destination
469 is a Vector, the "Reverse Gear" bit turns out to be a way to apply Iterative
470 or Cumulative Vector operations in reverse. `sv.add/rg r3.v, r4.v, r4.v`
471 for example will start at the opposite end of the Vector and push
472 a cumulative series of overlapping add operations into the Execution units of
473 the underlying hardware.
475 Other examples include shift-mask operations where a Vector of inserts
476 into a single destination register is required (see [[sv/bitmanip]], bmset),
477 as a way to construct
478 a value quickly from multiple arbitrary bit-ranges and bit-offsets.
479 Using the same register as both the source and destination, with Vectors
480 of different offsets masks and values to be inserted has multiple
481 applications including Video, cryptography and JIT compilation.
484 # * Vector of shift-offsets contained in RC (r12.v)
485 # * Vector of masks contained in RB (r8.v)
486 # * Vector of values to be masked-in in RA (r4.v)
487 # * Scalar destination RT (r0) to receive all mask-offset values
488 sv.bmset/mr r0, r4.v, r8.v, r12.v
490 Due to the Deterministic Scheduling,
491 Subtract and Divide are still permitted to be executed in this mode,
492 although from an algorithmic perspective it is strongly discouraged.
493 It would be better to use addition followed by one final subtract,
494 or in the case of divide, to get better accuracy, to perform a multiply
495 cascade followed by a final divide.
497 Note that single-operand or three-operand scalar-dest reduce is perfectly
498 well permitted: the programmer may still declare one register, used as
499 both a Vector source and Scalar destination, to be utilised as
500 the "accumulator". In the case of `sv.fmadds` and `sv.maddhw` etc
501 this naturally fits well with the normal expected usage of these
504 If an interrupt or exception occurs in the middle of the scalar mapreduce,
505 the scalar destination register **MUST** be updated with the current
506 (intermediate) result, because this is how ```Program Order``` is
507 preserved (Vector Loops are to be considered to be just another way of issuing instructions
508 in Program Order). In this way, after return from interrupt,
509 the scalar mapreduce may continue where it left off. This provides
510 "precise" exception behaviour.
512 Note that hardware is perfectly permitted to perform multi-issue
513 parallel optimisation of the scalar reduce operation: it's just that
514 as far as the user is concerned, all exceptions and interrupts **MUST**
517 ## Vector result reduce mode
519 Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base"
520 (Power ISA v3.0B) operation is leveraged, unmodified, to give the
521 *appearance* and *effect* of Reduction.
523 In Horizontal-First Mode, Vector-result reduction **requires**
524 the destination to be a Vector, which will be used to store
525 intermediary results.
527 Given that the tree-reduction schedule is deterministic,
528 Interrupts and exceptions
529 can therefore also be precise. The final result will be in the first
530 non-predicate-masked-out destination element, but due again to
531 the deterministic schedule programmers may find uses for the intermediate
534 When Rc=1 a corresponding Vector of co-resultant CRs is also
535 created. No special action is taken: the result and its CR Field
536 are stored "as usual" exactly as all other SVP64 Rc=1 operations.
538 Note that the Schedule only makes sense on top of certain instructions:
539 X-Form with a Register Profile of `RT,RA,RB` is fine. Like Scalar
540 Reduction, nothing is prohibited:
541 the results of execution on an unsuitable instruction may simply
542 not make sense. Many 3-input instructions (madd, fmadd) unlike Scalar
543 Reduction in particular do not make sense, but `ternlogi`, if used
546 **Parallel-Reduction with Predication**
548 To avoid breaking the strict RISC-paradigm, keeping the Issue-Schedule
549 completely separate from the actual element-level (scalar) operations,
550 Move operations are **not** included in the Schedule. This means that
551 the Schedule leaves the final (scalar) result in the first-non-masked
552 element of the Vector used. With the predicate mask being dynamic
553 (but deterministic) this result could be anywhere.
555 If that result is needed to be moved to a (single) scalar register
556 then a follow-up `sv.mv/sm=predicate rt, ra.v` instruction will be
557 needed to get it, where the predicate is the exact same predicate used
558 in the prior Parallel-Reduction instruction. For *some* implementations
559 this may be a slow operation. It may be better to perform a pre-copy
560 of the values, compressing them (VREDUCE-style) into a contiguous block,
561 which will guarantee that the result goes into the very first element
562 of the destination vector.
566 The simplest usage is to perform an overwrite, specifying all three
567 register operands the same.
570 sv.add/vr 8.v, 8.v, 8.v
572 The Reduction Schedule will issue the Parallel Tree Reduction spanning
573 registers 8 through 13, by adjusting the offsets to RT, RA and RB as
574 necessary (see "Parallel Reduction algorithm" in a later section).
576 A non-overwrite is possible as well but just as with the overwrite
577 version, only those destination elements necessary for storing
578 intermediary computations will be written to: the remaining elements
579 will **not** be overwritten and will **not** be zero'd.
582 sv.add/vr 0.v, 8.v, 8.v
584 ## Sub-Vector Horizontal Reduction
586 Note that when SVM is clear and SUBVL!=1 the sub-elements are
587 *independent*, i.e. they are mapreduced per *sub-element* as a result.
588 illustration with a vec2, assuming RA==RT, e.g `sv.add/mr/vec2 r4, r4, r16.v`
590 for i in range(0, VL):
591 # RA==RT in the instruction. does not have to be
592 iregs[RT].x = op(iregs[RT].x, iregs[RB+i].x)
593 iregs[RT].y = op(iregs[RT].y, iregs[RB+i].y)
595 Thus logically there is nothing special or unanticipated about
596 `SVM=0`: it is expected behaviour according to standard SVP64
599 By contrast, when SVM is set and SUBVL!=1, a Horizontal
600 Subvector mode is enabled, which behaves very much more
601 like a traditional Vector Processor Reduction instruction.
606 iregs[RT+i] = op(iregs[RA+i].x, iregs[RB+i].y)
611 iregs[RT+i] = op(iregs[RA+i].x, iregs[RB+i].y)
612 iregs[RT+i] = op(iregs[RT+i] , iregs[RB+i].z)
617 iregs[RT+i] = op(iregs[RA+i].x, iregs[RB+i].y)
618 iregs[RT+i] = op(iregs[RT+i] , iregs[RB+i].z)
619 iregs[RT+i] = op(iregs[RT+i] , iregs[RB+i].w)
621 In this mode, when Rc=1 the Vector of CRs is as normal: each result
622 element creates a corresponding CR element (for the final, reduced, result).
626 1. that the destination (RT) is inherently used as an "Accumulator"
627 register, and consequently the Sub-Vector Loop is interruptible.
628 If RT is a Scalar then as usual the main VL Loop terminates at the
629 first predicated element (or the first element if unpredicated).
630 2. that the Sub-Vector designation applies to RA and RB *but not RT*.
631 3. that the number of operations executed is one less than the Sub-vector
636 Data-dependent fail-on-first has two distinct variants: one for LD/ST
638 the other for arithmetic operations (actually, CR-driven)
639 ([[sv/normal]]) and CR operations ([[sv/cr_ops]]).
641 case the assumption is that vector elements are required appear to be
642 executed in sequential Program Order, element 0 being the first.
644 * LD/ST ffirst treats the first LD/ST in a vector (element 0) as an
645 ordinary one. Exceptions occur "as normal". However for elements 1
646 and above, if an exception would occur, then VL is **truncated** to the
648 * Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
649 CR-creating operation produces a result (including cmp). Similar to
650 branch, an analysis of the CR is performed and if the test fails, the
651 vector operation terminates and discards all element operations
652 above the current one (and the current one if VLi is not set),
653 and VL is truncated to either
654 the *previous* element or the current one, depending on whether
655 VLi (VL "inclusive") is set.
657 Thus the new VL comprises a contiguous vector of results,
658 all of which pass the testing criteria (equal to zero, less than zero).
660 The CR-based data-driven fail-on-first is new and not found in ARM
661 SVE or RVV. It is extremely useful for reducing instruction count,
662 however requires speculative execution involving modifications of VL
663 to get high performance implementations. An additional mode (RC1=1)
664 effectively turns what would otherwise be an arithmetic operation
665 into a type of `cmp`. The CR is stored (and the CR.eq bit tested
666 against the `inv` field).
667 If the CR.eq bit is equal to `inv` then the Vector is truncated and
669 Note that when RC1=1 the result elements are never stored, only the CRs.
671 VLi is only available as an option when `Rc=0` (or for instructions
672 which do not have Rc). When set, the current element is always
673 also included in the count (the new length that VL will be set to).
674 This may be useful in combination with "inv" to truncate the Vector
675 to *exclude* elements that fail a test, or, in the case of implementations
676 of strncpy, to include the terminating zero.
678 In CR-based data-driven fail-on-first there is only the option to select
679 and test one bit of each CR (just as with branch BO). For more complex
680 tests this may be insufficient. If that is the case, a vectorised crops
681 (crand, cror) may be used, and ffirst applied to the crop instead of to
682 the arithmetic vector.
684 One extremely important aspect of ffirst is:
686 * LDST ffirst may never set VL equal to zero. This because on the first
687 element an exception must be raised "as normal".
688 * CR-based data-dependent ffirst on the other hand **can** set VL equal
689 to zero. This is the only means in the entirety of SV that VL may be set
690 to zero (with the exception of via the SV.STATE SPR). When VL is set
691 zero due to the first element failing the CR bit-test, all subsequent
692 vectorised operations are effectively `nops` which is
693 *precisely the desired and intended behaviour*.
695 Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily
696 to a nonzero value for any implementation-specific reason. For example:
697 it is perfectly reasonable for implementations to alter VL when ffirst
698 LD or ST operations are initiated on a nonaligned boundary, such that
699 within a loop the subsequent iteration of that loop begins subsequent
700 ffirst LD/ST operations on an aligned boundary. Likewise, to reduce
701 workloads or balance resources.
703 CR-based data-dependent first on the other hand MUST not truncate VL
704 arbitrarily to a length decided by the hardware: VL MUST only be
705 truncated based explicitly on whether a test fails.
706 This because it is a precise test on which algorithms
709 ## Data-dependent fail-first on CR operations (crand etc)
711 Operations that actually produce or alter CR Field as a result
712 do not also in turn have an Rc=1 mode. However it makes no
713 sense to try to test the 4 bits of a CR Field for being equal
714 or not equal to zero. Moreover, the result is already in the
715 form that is desired: it is a CR field. Therefore,
716 CR-based operations have their own SVP64 Mode, described
719 There are two primary different types of CR operations:
721 * Those which have a 3-bit operand field (referring to a CR Field)
722 * Those which have a 5-bit operand (referring to a bit within the
725 More details can be found in [[sv/cr_ops]].
729 Pred-result mode may not be applied on CR-based operations.
731 Although CR operations (mtcr, crand, cror) may be Vectorised,
732 predicated, pred-result mode applies to operations that have
733 an Rc=1 mode, or make sense to add an RC1 option.
735 Predicate-result merges common CR testing with predication, saving on
736 instruction count. In essence, a Condition Register Field test
737 is performed, and if it fails it is considered to have been
738 *as if* the destination predicate bit was zero. Given that
739 there are no CR-based operations that produce Rc=1 co-results,
740 there can be no pred-result mode for mtcr and other CR-based instructions
742 Arithmetic and Logical Pred-result, which does have Rc=1 or for which
743 RC1 Mode makes sense, is covered in [[sv/normal]]
747 CRs are slightly more involved than INT or FP registers due to the
748 possibility for indexing individual bits (crops BA/BB/BT). Again however
749 the access pattern needs to be understandable in relation to v3.0B / v3.1B
750 numbering, with a clear linear relationship and mapping existing when
753 ## CR EXTRA mapping table and algorithm <a name="cr_extra"></a>
755 Numbering relationships for CR fields are already complex due to being
756 in BE format (*the relationship is not clearly explained in the v3.0B
757 or v3.1 specification*). However with some care and consideration
758 the exact same mapping used for INT and FP regfiles may be applied,
759 just to the upper bits, as explained below. The notation
760 `CR{field number}` is used to indicate access to a particular
761 Condition Register Field (as opposed to the notation `CR[bit]`
762 which accesses one bit of the 32 bit Power ISA v3.0B
765 `CR{n}` refers to `CR0` when `n=0` and consequently, for CR0-7, is defined, in v3.0B pseudocode, as:
767 CR{7-n} = CR[32+n*4:35+n*4]
769 For SVP64 the relationship for the sequential
770 numbering of elements is to the CR **fields** within
771 the CR Register, not to individual bits within the CR register.
773 In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (0:2)
774 select one of the 8 CRs; the bottom 2 bits (3:4) select one of 4 bits
775 *in* that CR (EQ/LT/GT/SO). The numbering was determined (after 4 months of
776 analysis and research) to be as follows:
778 CR_index = 7-(BA>>2) # top 3 bits but BE
779 bit_index = 3-(BA & 0b11) # low 2 bits but BE
780 CR_reg = CR{CR_index} # get the CR
781 # finally get the bit from the CR.
782 CR_bit = (CR_reg & (1<<bit_index)) != 0
784 When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
785 applies, **not** the CR\_bit portion (bits 3-4):
790 spec = EXTRA2<<1 | 0b0
792 # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
793 return ((BA >> 2)<<6) | # hi 3 bits shifted up
794 (spec[1:2]<<4) | # to make room for these
795 (BA & 0b11) # CR_bit on the end
797 # scalar constructs "00 spec[1:2] BA[0:4]"
798 return (spec[1:2] << 5) | BA
800 Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
801 algorithm to determine CR\_reg is modified to as follows:
803 CR_index = 7-(BA>>2) # top 3 bits but BE
805 # vector mode, 0-124 increments of 4
806 CR_index = (CR_index<<4) | (spec[1:2] << 2)
808 # scalar mode, 0-32 increments of 1
809 CR_index = (spec[1:2]<<3) | CR_index
810 # same as for v3.0/v3.1 from this point onwards
811 bit_index = 3-(BA & 0b11) # low 2 bits but BE
812 CR_reg = CR{CR_index} # get the CR
813 # finally get the bit from the CR.
814 CR_bit = (CR_reg & (1<<bit_index)) != 0
816 Note here that the decoding pattern to determine CR\_bit does not change.
818 Note: high-performance implementations may read/write Vectors of CRs in
819 batches of aligned 32-bit chunks (CR0-7, CR7-15). This is to greatly
820 simplify internal design. If instructions are issued where CR Vectors
821 do not start on a 32-bit aligned boundary, performance may be affected.
823 ## CR fields as inputs/outputs of vector operations
825 CRs (or, the arithmetic operations associated with them)
826 may be marked as Vectorised or Scalar. When Rc=1 in arithmetic operations that have no explicit EXTRA to cover the CR, the CR is Vectorised if the destination is Vectorised. Likewise if the destination is scalar then so is the CR.
828 When vectorized, the CR inputs/outputs are sequentially read/written
829 to 4-bit CR fields. Vectorised Integer results, when Rc=1, will begin
830 writing to CR8 (TBD evaluate) and increase sequentially from there.
833 * implementations may rely on the Vector CRs being aligned to 8. This
834 means that CRs may be read or written in aligned batches of 32 bits
835 (8 CRs per batch), for high performance implementations.
836 * scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not
837 overwritten by vector Rc=1 operations except for very large VL
838 * CR-based predication, from CR32, is also not interfered with
839 (except by large VL).
841 However when the SV result (destination) is marked as a scalar by the
842 EXTRA field the *standard* v3.0B behaviour applies: the accompanying
843 CR when Rc=1 is written to. This is CR0 for integer operations and CR1
846 Note that yes, the CR Fields are genuinely Vectorised. Unlike in SIMD VSX which
847 has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
848 v3.0B scalar operations produce a **tuple** of element results: the
849 result of the operation as one part of that element *and a corresponding
850 CR element*. Greatly simplified pseudocode:
853 # calculate the vector result of an add
854 iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
855 # now calculate CR bits
856 CRs{8+i}.eq = iregs[RT+i] == 0
857 CRs{8+i}.gt = iregs[RT+i] > 0
860 If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
861 then a followup instruction must be performed, setting "reduce" mode on
862 the Vector of CRs, using cr ops (crand, crnor) to do so. This provides far
863 more flexibility in analysing vectors than standard Vector ISAs. Normal
864 Vector ISAs are typically restricted to "were all results nonzero" and
865 "were some results nonzero". The application of mapreduce to Vectorised
866 cr operations allows far more sophisticated analysis, particularly in
867 conjunction with the new crweird operations see [[sv/cr_int_predication]].
869 Note in particular that the use of a separate instruction in this way
870 ensures that high performance multi-issue OoO inplementations do not
871 have the computation of the cumulative analysis CR as a bottleneck and
872 hindrance, regardless of the length of VL.
875 SVP64 [[sv/branches]] may be used, even when the branch itself is to
876 the following instruction. The combined side-effects of CTR reduction
877 and VL truncation provide several benefits.
879 (see [[discussion]]. some alternative schemes are described there)
881 ## Rc=1 when SUBVL!=1
883 sub-vectors are effectively a form of Packed SIMD (length 2 to 4). Only 1 bit of
884 predicate is allocated per subvector; likewise only one CR is allocated
887 This leaves a conundrum as to how to apply CR computation per subvector,
888 when normally Rc=1 is exclusively applied to scalar elements. A solution
889 is to perform a bitwise OR or AND of the subvector tests. Given that
890 OE is ignored in SVP64, this field may (when available) be used to select OR or
893 ### Table of CR fields
895 CRn is the notation used by the OpenPower spec to refer to CR field #i,
896 so FP instructions with Rc=1 write to CR1 (n=1).
898 CRs are not stored in SPRs: they are registers in their own right.
899 Therefore context-switching the full set of CRs involves a Vectorised
900 mfcr or mtcr, using VL=8 to do so. This is exactly as how
901 scalar OpenPOWER context-switches CRs: it is just that there are now
904 The 64 SV CRs are arranged similarly to the way the 128 integer registers
905 are arranged. TODO a python program that auto-generates a CSV file
906 which can be included in a table, which is in a new page (so as not to
907 overwhelm this one). [[svp64/cr_names]]
911 Instructions are broken down by Register Profiles as listed in the
912 following auto-generated page: [[opcode_regs_deduped]]. These tables,
913 despite being auto-generated, are part of the Specification.
915 # SV pseudocode illilustration
917 ## Single-predicated Instruction
919 illustration of normal mode add operation: zeroing not included, elwidth
920 overrides not included. if there is no predicate, it is set to all 1s
922 function op_add(rd, rs1, rs2) # add not VADD!
923 int i, id=0, irs1=0, irs2=0;
924 predval = get_pred_val(FALSE, rd);
925 for (i = 0; i < VL; i++)
926 STATE.srcoffs = i # save context
927 if (predval & 1<<i) # predication uses intregs
928 ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
929 if (!int_vec[rd].isvec) break;
930 if (rd.isvec) { id += 1; }
931 if (rs1.isvec) { irs1 += 1; }
932 if (rs2.isvec) { irs2 += 1; }
933 if (id == VL or irs1 == VL or irs2 == VL)
935 # end VL hardware loop
936 STATE.srcoffs = 0; # reset
940 This has several modes:
943 * RT.v = RA.v RB.s (and RA.s RB.v)
946 * RT.s = RA.v RB.s (and RA.s RB.v)
949 All of these may be predicated. Vector-Vector is straightfoward.
950 When one of source is a Vector and the other a Scalar, it is clear that
951 each element of the Vector source should be added to the Scalar source,
952 each result placed into the Vector (or, if the destination is a scalar,
953 only the first nonpredicated result).
955 The one that is not obvious is RT=vector but both RA/RB=scalar.
956 Here this acts as a "splat scalar result", copying the same result into
957 all nonpredicated result elements. If a fixed destination scalar was
958 intended, then an all-Scalar operation should be used.
960 See <https://bugs.libre-soc.org/show_bug.cgi?id=552>
962 # Assembly Annotation
964 Assembly code annotation is required for SV to be able to successfully
965 mark instructions as "prefixed".
967 A reasonable (prototype) starting point:
973 * ew=8/16/32 - element width
974 * sew=8/16/32 - source element width
976 * mode=mr/satu/sats/crpred
977 * pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
979 similar to x86 "rex" prefix.
981 For actual assembler:
983 sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s
987 * m={pred}: predicate mask mode
988 * sm={pred}: source-predicate mask mode (only allowed in Twin-predication)
989 * vec{N}: vec2 OR vec3 OR vec4 - sets SUBVL=2/3/4
990 * ew={N}: ew=8/16/32 - sets elwidth override
991 * sw={N}: sw=8/16/32 - sets source elwidth override
992 * ff={xx}: see fail-first mode
993 * pr={xx}: see predicate-result mode
994 * sat{x}: satu / sats - see saturation mode
995 * mr: see map-reduce mode
996 * mr.svm see map-reduce with sub-vector mode
997 * crm: see map-reduce CR mode
998 * crm.svm see map-reduce CR with sub-vector mode
999 * sz: predication with source-zeroing
1000 * dz: predication with dest-zeroing
1005 - pm=lt/gt/le/ge/eq/ne/so/ns
1008 - ff=lt/gt/le/ge/eq/ne/so/ns
1014 - mr OR crm: "normal" map-reduce mode or CR-mode.
1015 - mr.svm OR crm.svm: when vec2/3/4 set, sub-vector mapreduce is enabled
1017 # Parallel-reduction algorithm
1019 The principle of SVP64 is that SVP64 is a fully-independent
1020 Abstraction of hardware-looping in between issue and execute phases
1021 that has no relation to the operation it issues.
1022 Additional state cannot be saved on context-switching beyond that
1023 of SVSTATE, making things slightly tricky.
1025 Executable demo pseudocode, full version
1026 [here](https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_preduce.py;hb=HEAD)
1029 [[!inline raw="yes" pages="openpower/sv/preduce.py" ]]
1032 This algorithm works by noting when data remains in-place rather than
1033 being reduced, and referring to that alternative position on subsequent
1034 layers of reduction. It is re-entrant. If however interrupted and
1035 restored, some implementations may take longer to re-establish the
1038 Its application by default is that:
1040 * RA, FRA or BFA is the first register as the first operand
1041 (ci index offset in the above pseudocode)
1042 * RB, FRB or BFB is the second (co index offset)
1043 * RT (result) also uses ci **if RA==RT**
1045 For more complex applications a REMAP Schedule must be used
1047 *Programmers's note:
1048 if passed a predicate mask with only one bit set, this algorithm
1049 takes no action, similar to when a predicate mask is all zero.*
1051 *Implementor's Note: many SIMD-based Parallel Reduction Algorithms are
1052 implemented in hardware with MVs that ensure lane-crossing is minimised.
1053 The mistake which would be catastrophic to SVP64 to make is to then
1054 limit the Reduction Sequence for all implementors
1055 based solely and exclusively on what one
1056 specific internal microarchitecture does.
1057 In SIMD ISAs the internal SIMD Architectural design is exposed and imposed on the programmer. Cray-style Vector ISAs on the other hand provide convenient,
1058 compact and efficient encodings of abstract concepts.*
1059 **It is the Implementor's responsibility to produce a design
1060 that complies with the above algorithm,
1061 utilising internal Micro-coding and other techniques to transparently
1062 insert micro-architectural lane-crossing Move operations
1063 if necessary or desired, to give the level of efficiency or performance
1066 # Element-width overrides <a name="elwidth"> </>
1068 Element-width overrides are best illustrated with a packed structure
1069 union in the c programming language. The following should be taken
1070 literally, and assume always a little-endian layout:
1077 uint8_t actual_bytes[8];
1080 elreg_t int_regfile[128];
1082 get_polymorphed_reg(reg, bitwidth, offset):
1084 res.l = 0; // TODO: going to need sign-extending / zero-extending
1086 reg.b = int_regfile[reg].b[offset]
1087 elif bitwidth == 16:
1088 reg.s = int_regfile[reg].s[offset]
1089 elif bitwidth == 32:
1090 reg.i = int_regfile[reg].i[offset]
1091 elif bitwidth == 64:
1092 reg.l = int_regfile[reg].l[offset]
1095 set_polymorphed_reg(reg, bitwidth, offset, val):
1097 # not a vector: first element only, overwrites high bits
1098 int_regfile[reg].l[0] = val
1100 int_regfile[reg].b[offset] = val
1101 elif bitwidth == 16:
1102 int_regfile[reg].s[offset] = val
1103 elif bitwidth == 32:
1104 int_regfile[reg].i[offset] = val
1105 elif bitwidth == 64:
1106 int_regfile[reg].l[offset] = val
1108 In effect the GPR registers r0 to r127 (and corresponding FPRs fp0
1109 to fp127) are reinterpreted to be "starting points" in a byte-addressable
1110 memory. Vectors - which become just a virtual naming construct - effectively
1113 It is extremely important for implementors to note that the only circumstance
1114 where upper portions of an underlying 64-bit register are zero'd out is
1115 when the destination is a scalar. The ideal register file has byte-level
1116 write-enable lines, just like most SRAMs, in order to avoid READ-MODIFY-WRITE.
1118 An example ADD operation with predication and element width overrides:
1120 for (i = 0; i < VL; i++)
1121 if (predval & 1<<i) # predication
1122 src1 = get_polymorphed_reg(RA, srcwid, irs1)
1123 src2 = get_polymorphed_reg(RB, srcwid, irs2)
1124 result = src1 + src2 # actual add here
1125 set_polymorphed_reg(RT, destwid, ird, result)
1126 if (!RT.isvec) break
1127 if (RT.isvec) { id += 1; }
1128 if (RA.isvec) { irs1 += 1; }
1129 if (RB.isvec) { irs2 += 1; }
1131 Thus it can be clearly seen that elements are packed by their
1132 element width, and the packing starts from the source (or destination)
1133 specified by the instruction.
1135 # Twin (implicit) result operations
1137 Some operations in the Power ISA already target two 64-bit scalar
1138 registers: `lq` for example, and LD with update.
1139 Some mathematical algorithms are more
1140 efficient when there are two outputs rather than one, providing
1141 feedback loops between elements (the most well-known being add with
1142 carry). 64-bit multiply
1143 for example actually internally produces a 128 bit result, which clearly
1144 cannot be stored in a single 64 bit register. Some ISAs recommend
1145 "macro op fusion": the practice of setting a convention whereby if
1146 two commonly used instructions (mullo, mulhi) use the same ALU but
1147 one selects the low part of an identical operation and the other
1148 selects the high part, then optimised micro-architectures may
1149 "fuse" those two instructions together, using Micro-coding techniques,
1152 The practice and convention of macro-op fusion however is not compatible
1153 with SVP64 Horizontal-First, because Horizontal Mode may only
1154 be applied to a single instruction at a time, and SVP64 is based on
1155 the principle of strict Program Order even at the element
1156 level. Thus it becomes
1157 necessary to add explicit more complex single instructions with
1158 more operands than would normally be seen in the average RISC ISA
1159 (3-in, 2-out, in some cases). If it
1160 was not for Power ISA already having LD/ST with update as well as
1161 Condition Codes and `lq` this would be hard to justify.
1163 With limited space in the `EXTRA` Field, and Power ISA opcodes
1164 being only 32 bit, 5 operands is quite an ask. `lq` however sets
1165 a precedent: `RTp` stands for "RT pair". In other words the result
1166 is stored in RT and RT+1. For Scalar operations, following this
1167 precedent is perfectly reasonable. In Scalar mode,
1168 `madded` therefore stores the two halves of the 128-bit multiply
1171 What, then, of `sv.madded`? If the destination is hard-coded to
1172 RT and RT+1 the instruction is not useful when Vectorised because
1173 the output will be overwritten on the next element. To solve this
1174 is easy: define the destination registers as RT and RT+MAXVL
1175 respectively. This makes it easy for compilers to statically allocate
1176 registers even when VL changes dynamically.
1178 Bear in mind that both RT and RT+MAXVL are starting points for Vectors,
1179 and bear in mind that element-width overrides still have to be taken
1180 into consideration, the starting point for the implicit destination
1181 is best illustrated in pseudocode:
1184 for (i = 0; i < VL; i++)
1185 if (predval & 1<<i) # predication
1186 src1 = get_polymorphed_reg(RA, srcwid, irs1)
1187 src2 = get_polymorphed_reg(RB, srcwid, irs2)
1188 src2 = get_polymorphed_reg(RC, srcwid, irs3)
1189 result = src1*src2 + src2
1190 destmask = (2<<destwid)-1
1191 # store two halves of result, both start from RT.
1192 set_polymorphed_reg(RT, destwid, ird , result&destmask)
1193 set_polymorphed_reg(RT, destwid, ird+MAXVL, result>>destwid)
1194 if (!RT.isvec) break
1195 if (RT.isvec) { id += 1; }
1196 if (RA.isvec) { irs1 += 1; }
1197 if (RB.isvec) { irs2 += 1; }
1198 if (RC.isvec) { irs3 += 1; }
1200 The significant part here is that the second half is stored
1201 starting not from RT+MAXVL at all: it is the *element* index
1202 that is offset by MAXVL, both halves actually starting from RT.
1203 If VL is 3, MAXVL is 5, RT is 1, and dest elwidth is 32 then the elements
1204 RT0 to RT2 are stored:
1207 r0 unchanged unchanged
1212 r5 unchanged unchanged
1214 Note that all of the LO halves start from r1, but that the HI halves
1215 start from half-way into r3. The reason is that with MAXVL bring
1216 5 and elwidth being 32, this is the 5th element
1217 offset (in 32 bit quantities) counting from r1.
1219 *Programmer's note: accessing registers that have been placed
1220 starting on a non-contiguous boundary (half-way along a scalar
1221 register) can be inconvenient: REMAP can provide an offset but
1222 it requires extra instructions to set up. A simple solution
1223 is to ensure that MAXVL is rounded up such that the Vector
1224 ends cleanly on a contiguous register boundary. MAXVL=6 in
1225 the above example would achieve that*
1227 Additional DRAFT Scalar instructions in 3-in 2-out form
1228 with an implicit 2nd destination:
1230 * [[isa/svfixedarith]]