openpower/sv/svp64-single.mdwn

   1 # TODO
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=905>
   4
   5 encodings concepts:
   6
   7 * 24 bits available
   8 * vectors not applicable thus EXTRA4 may bring 4 bits (CR Fields) quantity 3of
   9   for a total of 12 bits. GPR/FPR/VR 3 bits extends VR to 512 regs (!) and
  10   GPR/FPR to 256 (!)
  11 * elwidth src/dest is 2x2 for a total 4 bits
  12 * single predicate mask (one bit) is 1 for type
  13   (GPR/VR and CRfield), 3 for source, totals another 4 bits
  14
  15 totals 20 bits leaving 4 for a "Mode".
  16
  17 * arithmetic can have saturation (2 bits?)
  18 * LD/ST-update needs Post-Increment, others incl. SEA (Signed Effective Address)
  19   another bit adds CIA for PC-relative
  20
  21 potentially this leaves 2 bits for SUBVL.  an advantage of that is
  22 that VSX could be over-ridden to have the number of PackedSIMD
  23 element operations redefined?
  24