openpower/sv/svp64-single.mdwn

   1 # TODO
   2
   3 * <https://bugs.libre-soc.org/show_bug.cgi?id=905>
   4
   5 encodings concepts:
   6
   7 * 24 bits available
   8 * vectors not applicable thus EXTRA4 may bring 4 bits (CR Fields) quantity 3of
   9   for a total of 12 bits.
  10 * elwidth src/dest is 2x4 for a total 4 bits
  11 * single predicate mask (one bit) is 1 for type, 3 for source, totals another 4 bits
  12
  13 totals 20 bits leaving 4 for a "Mode".
  14
  15 * arithmetic can have saturation
  16 * LD/ST-update needs Post-Increment, others incl. SEA (Signed Effective Address)
  17   another bit adds CIA for PC-relative