1 # SVP64 Zero-Overhead Loop Prefix Subsystem
4 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[Power|openpower]] v3.0B [[ISA|openpower/isa/]].
9 Credits and acknowledgements:
17 * NLnet Foundation, for funding
18 * OpenPOWER Foundation
23 * IBM for the Power ISA itself
28 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
29 * [[svp64/discussion]]
31 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
34 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
35 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
36 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045> External RFC ls010
37 * [[sv/branches]] chapter
47 Simple-V is a type of Vectorization best described as a "Prefix Loop
48 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and
49 to the 8086 `REP`[^bib_rep] Prefix instruction. More advanced features are similar
50 to the Z80 `CPIR`[^bib_cpir] instruction.
52 [^bib_ldir]: [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
53 [^bib_cpir]: [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)
54 [^bib_rep]: [8086 REP](https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz)
56 Except where explicitly stated all bit numbers remain as in the rest of
57 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
58 the left and counting up as you move rightwards to the LSB end). All bit
59 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
60 **All register numbering and element numbering however is LSB0 ordering**
61 which is a different convention from that used elsewhere in the Power ISA.
63 The SVP64 prefix always comes before the suffix in PC order and must be
64 considered an independent "Defined Word-instruction"[^dwi] that augments the behaviour of
65 the following instruction (also a Defined Word-instruction), but does **not** change the actual Decoding
66 of that following instruction just because it is Prefixed. Unlike EXT100-163,
67 where the Suffix is considered an entirely new Opcode Space,
68 SVP64-Prefixed instructions **MUST NEVER** be treated or regarded
69 as a different Opcode Space.
71 [^dwi]: Defined Word-instruction: Power ISA v3.1 Section 1.6
73 *Architectural note: Treating the SVP64 Prefix as an "Independent" 64-bit Encoding Space and attempting
74 to allocate non-Orthogonal Opcodes within it will result
75 in catastrophic unviability of Simple-V. The Orthogonality of the Scalar vs Prefixed-Scalar
76 spaces has to be considered inviolate, to the extent that even RESERVED spaces must be
77 kept identical. The complexity at the Decode Phase by violating the RISC paradigm inherent
78 in Simple-V will be unimplementable*
80 Two apparent exceptions to the above hard rule exist: SV
81 Branch-Conditional operations and LD/ST-update "Post-Increment"
82 Mode. Post-Increment was considered sufficiently high priority
83 (significantly reducing hot-loop instruction count) that one bit in
84 the Prefix is reserved for it (*Note the intention to release that bit
85 and move Post-Increment instructions to EXT2xx, as part of [[sv/rfc/ls011]]*).
86 Vectorized Branch-Conditional operations "embed" the original Scalar
87 Branch-Conditional behaviour into a much more advanced variant that is
88 highly suited to High-Performance Computation (HPC), Supercomputing,
89 and parallel GPU Workloads.
91 *Architectural Resource Allocation note: at present it is possible to perform
92 partial parallel decode of the SVP64 24-bit Encoding Area at the same time
93 as decoding of the Suffix. Multi-Issue Implementations may even
94 Decode multiple 32-bit words in parallel and follow up with a second
95 cycle of joining Prefix and Suffix "after-the-fact".
96 Mixing and overlaying 64-bit Opcode Encodings into the
97 {SVP64 24-bit Prefix}{Defined Word-instruction} space creates
98 a hard dependency that catastrophically damages Multi-Issue Decoding by
99 greatly complexifying Parallel Instruction-Length Detection.
100 Therefore it has to be prohibited to accept RFCs
101 which fundamentally violate the following hard requirement: **under no circumstances**
102 must the use of SVP64 24-bit Suffixes **also** imply a different Opcode space
103 from **any** non-prefixed Word, even RESERVED or Illegal Words.*
105 Subset implementations in hardware are permitted, as long as certain
106 rules are followed, allowing for full soft-emulation including future
107 revisions. Compliancy Subsets exist to ensure minimum levels of binary
108 interoperability expectations within certain environments. Details in
109 the [[svp64/appendix]].
111 ## SVP64 encoding features
113 A number of features need to be compacted into a very small space of
116 * Independent per-register Scalar/Vector tagging and range extension on
118 * Element width overrides on both source and destination
119 * Predication on both source and destination
120 * Two different sources of predication: INT and CR Fields
121 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
124 Different classes of operations require different formats. The earlier
125 sections cover the common formats and the five separate modes have their own
127 * CR operations (crops),
128 * Arithmetic/Logical (termed "normal"),
129 * Load/Store Immediate,
130 * Load/Store Indexed,
131 * Branch-Conditional.
133 ## Definition of Reserved in this spec.
135 For the new fields added in SVP64, instructions that have any of their
136 fields set to a reserved value must cause an illegal instruction trap,
137 to allow emulation of future instruction sets, or for subsets of SVP64 to
138 be implemented in hardware and the rest emulated. This includes SVP64
139 SPRs: reading or writing values which are not supported in hardware
140 must also raise illegal instruction traps in order to allow emulation.
141 Unless otherwise stated, reserved values are always all zeros.
143 This is unlike OpenPower ISA v3.1, which in many instances does not
144 require a trap if reserved fields are nonzero, instead relying on software
145 to avoid use of such fields. Where the standard Power
146 ISA definition is intended the red keyword `RESERVED` is used.
148 ## Definition of "PO9-Prefixed"
150 Used in the context of "A PO9-Prefixed Word" this is a new area similar to EXT100-163
151 that is shared between SVP64-Single, SVP64, 32 Vectorizable new Opcode areas
152 EXT200-231, one RESERVED 57-bit future Opcode space, and three new Unvectorizable
153 RESERVED 32-bit future Opcode spaces. See [[sv/po9_encoding]].
155 ## Definition of "SVP64-Prefix"
157 A 24-bit RISC-Paradigm Encoding area for Loop-Augmentation of the following
158 "Defined Word-instruction-instruction".
159 Used in the context of "An SVP64-Prefixed Defined Word-instruction", as separate and
160 distinct from the 32-bit PO9-Prefix that holds a 24-bit SVP64 Prefix.
162 ## Definition of "Vectorizable" and "Unvectorizable"
164 "Vectorizable" Defined Word-instructions are Scalar instructions that
165 benefit from SVP64 Loop-Prefixing.
166 Conversely, any operation that inherently makes no sense if repeated in a
167 Vector Loop is termed
168 "Unvectorizable" or "Unvectorized". Examples include `sc` or `sync`
169 which have no registers. `mtmsr` is also classed as Unvectorizable
170 because there is only one `MSR`.
172 UnVectorized instructions are required to be detected as such if
173 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
176 *Architectural Note: Given that a "pre-classification" Decode Phase is
177 required (identifying whether the Suffix - Defined Word-instruction - is
178 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
179 adding "Unvectorized" to this phase is not unreasonable.*
181 Vectorizable Defined Word-instructions are **required** to be Vectorized,
182 or they may not be permitted to be added at all to the Power ISA as Defined
185 *Engineering note: implementations may not choose to add Defined Word-instructions
186 without also adding hardware support for SVP64-Prefixing of the same.*
188 *ISA Working Group note: Vectorized PackedSIMD instructions if ever proposed
189 should be considered Unvectorizable and except in extreme mitigating circumstances
192 ## Definition of Strict Element-Level Execution Order<a name="svp64_eeo"> </a>
194 Where Instruction Execution Order[^ieo] guarantees the appearance of sequential
195 execution of instructions, Simple-V requires a corresponding guarantee for Elements
196 because in Simple-V Execution of Elements is synonymous with Execution of
199 [^ieo]: Strict Instruction Execution Order is defined in Public v3.1 Book I Section 2.2
201 ## Precise Interrupt Guarantees
203 Strict Instruction Execution Order is defined as giving the appearance, as far
204 as programs are concerned, that instructions were executed
205 strictly in the sequence that they occurred. A "Precise"
207 Micro-architecture goes to considerable lengths to ensure that
210 Many Vector ISAs allow interrupts to occur in the middle of
211 processing of large Vector operations, only under the condition
212 that partial results are cleanly discarded, and continuation on return
213 from the Trap Handler will restart the entire operation.
214 The reason is that saving of full Architectural State is
215 not practical. An example would be a Floating-Point Horizontal Sum instruction
216 (very common in Vector ISAs) or a Dot Product instruction
217 that specifies a higher degree of accuracy for the *internal*
218 accumulator than the registers.
220 Simple-V operates on an entirely different paradigm from traditional
221 Vector ISAs: as a "Sub-Execution Context", where "Elements" are synonymous
222 with Scalar instructions. With this in mind
223 implementations must observe Strict **Element**-Level Execution Order[[#svp64_eeo]]
225 *Any* element is Interruptible, and Architectural State may
226 be fully preserved and restored regardless of that same State.
228 *Engineering note: implementations are permitted have higher latency to
229 perform context-switching (particularly if REMAP
232 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
233 but the full SVP64 Architectural State may be saved and
234 restored through manual copying of `SVSTATE` (and the four
235 REMAP SPRs if in use at the time, which may be determined by
236 `SVSTATE[32:46]` being non-zero).
238 *Programmer's note: Trap Handlers (and any stack-based context save/restore)
239 must avoid the use of SVP64 Prefixed instructions to perform the necessary
240 save/restore of Simple-V Architectural State (SPR SVSTATE),
241 just as use of FPRs and VSRs is presently avoided.
242 However once saved, and set to known-good, SVP64 Prefixed instructions
243 may be used to save/restore GPRs, SPRs, FPRs and other state.*
245 *Programmer's note: SVSHAPE0-3 alters Element Execution Order, but only
246 if activated in SVSHAPE. It is therefore technically possible in a Trap
247 Handler to save SVSTATE (`mfspr t0, SVSTATE`), then clear bits 32-46.
248 At this point it becomes safe to use SVP64 to save sequential batches
249 of SPRs (`setvli MAXVL=VL=4; sv.mfspr *t0, *SVSHAPE0`)*
251 The only major caveat for REMAP is that
252 after an explicit change to
253 Architectural State caused by writing to the
254 Simple-V SPRs, some implementations may find
255 it easier to take longer to calculate where in a given Schedule
256 the re-mapping Indices were. Obvious examples include Interrupts occuring
257 in the middle of a non-RADIX2 Matrix Multiply Schedule (5x3 by 3x3
259 will force some implementations to perform divide and modulo
262 An additional caveat involves Condition Register Fields
263 when also used as Predicate Masks. An operation that
264 overwrites the same CR Fields that are simultaneously
265 being used as a Predicate Mask should exercise extreme care
266 if the overwritten CR field element was needed by a
267 subsequent Element for its Predicate Mask bit.
269 Some implementations may deploy Cray's technique of
270 "Vector Chaining" (including in this case reading the CR field
271 containing the Predicate bit until the very last moment),
272 and consequently avoiding the risk of
273 overwrite is the responsibility of the Programmer.
274 `hphint` may be used here to good effect.
275 Extra Special care is particularly needed here when using REMAP
276 and also Vertical-First Mode.
278 The simplest option is to use Integer Predicate Masks but the
279 caveats are stricter:
281 * In Vertical-First loops Programmers **must not** write to any
282 Integers (r3, r0, r31) used as Predicate Masks. Doing so
283 is `UNDEFINED` behaviour.
284 * An **entire** Vector is held up on Horizontal-First Mode if the
285 Integer Predicate is still in in-flight Reservation Stations
286 or pipelines. Speculative Vector Chained Execution mitigates delays
287 but can be heavy on Reservation Station resources.
289 ## Register files, elements, and Element-width Overrides
291 The relationship between register files, elements, and element-width
292 overrides is expressed as follows:
294 * register files are considered to be *byte-level* contiguous SRAMs,
295 accessed exclusively in Little-Endian Byte-Order at all times
296 * elements are sequential contiguous unbounded arrays starting at the "address"
297 of any given 64-bit GPR or FPR, numbered from 0 as the first,
298 "spilling" into numerically-sequentially-increasing GPRs
299 * element-width overrides set the width of the *elements* in the
300 sequentially-numbered contiguous array.
302 The relationship is best defined in Canonical form, below, in ANSI c as a
303 union data structure. A key difference is that VSR elements are bounded
304 fixed at 128-bit, where SVP64 elements are conceptually unbounded and
305 only limited by the Maximum Vector Length.
307 *Future specification note: SVP64 may be defined on top of VSRs in future.
308 At which point VSX also gains conceptually unbounded VSR register elements*
310 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR
311 Register files are expanded from 32 to 128 entries, and the number of
312 CR Fields expanded from CR0-CR7 to CR0-CR127. (Note: A future version
313 of SVP64 is anticipated to extend the VSR register file).
315 Memory access remains exactly the same: the effects of `MSR.LE` remain
316 exactly the same, affecting as they already do and remain **only**
317 on the Load and Store memory-register operation byte-order, and having
318 nothing to do with the ordering of the contents of register files or
319 register-register arithmetic or logical operations.
321 The only major impact on Arithmetic and Logical operations is that all
322 Scalar operations are defined, where practical and workable, to have
323 three new widths: elwidth=32, elwidth=16, elwidth=8.
325 *Architectural note: a future revision of SVP64 for VSX may have entirely
326 different definitions of possible elwidths.*
329 elwidth=64 is the pre-existing (Scalar) behaviour which remains 100%
330 unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit
331 variant of `addi`, but the sole exclusive difference is the width.
332 *In no way* is the actual `addi` instruction fundamentally altered
333 to become an entirely different operation (such as a subtract or multiply).
334 FP Operations elwidth overrides are also defined, as explained in
335 the [[svp64/appendix]].
337 To be absolutely clear:
340 There are no conceptual arithmetic ordering or other changes over the
341 Scalar Power ISA definitions to registers or register files or to
342 arithmetic or Logical Operations, beyond element-width subdivision
346 numbering is naturally **LSB0-sequentially-incrementing from zero, not
347 MSB0-incrementing** including when element-width overrides are used,
348 at which point the elements progress through each register
349 sequentially from the LSB end
350 (confusingly numbered the highest in MSB0 ordering) and progress
351 incrementally to the MSB end (confusingly numbered the lowest in
354 When exclusively using MSB0-numbering, SVP64 becomes unnecessarily complex
355 to both express and subsequently understand: the required conditional
356 subtractions from 63, 31, 15 and 7 needed to express the fact that
357 elements are LSB0-sequential unfortunately become a hostile minefield,
358 obscuring both intent and meaning. Therefore for the purposes of this
359 section the more natural **LSB0 numbering is assumed** and it is left
360 to the reader to translate to MSB0 numbering.
362 The Canonical specification for how element-sequential numbering and
363 element-width overrides is defined is expressed in the following c
364 structure, assuming a Little-Endian system, and naturally using LSB0
365 numbering everywhere because the ANSI c specification is inherently LSB0.
366 Note the deliberate similarity to how VSX register elements are defined,
367 from Figure 97, Book I, Section 6.3, Page 258:
372 uint8_t actual_bytes[8];
373 // all of these are very deliberately unbounded arrays
374 // that intentionally "wrap" into subsequent actual_bytes...
375 uint8_t bytes[]; // elwidth 8
376 uint16_t hwords[]; // elwidth 16
377 uint32_t words[]; // elwidth 32
378 uint64_t dwords[]; // elwidth 64
382 // ... here, as packed statically-defined GPRs.
383 elreg_t int_regfile[128];
385 // use element 0 as the destination
386 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
388 case 64: el->dwords[0] = int_regfile[gpr].dwords[element];
389 case 32: el->words[0] = int_regfile[gpr].words[element];
390 case 16: el->hwords[0] = int_regfile[gpr].hwords[element];
391 case 8 : el->bytes[0] = int_regfile[gpr].bytes[element];
395 // use element 0 as the source
396 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
398 case 64: int_regfile[gpr].dwords[element] = el->dwords[0];
399 case 32: int_regfile[gpr].words[element] = el->words[0];
400 case 16: int_regfile[gpr].hwords[element] = el->hwords[0];
401 case 8 : int_regfile[gpr].bytes[element] = el->bytes[0];
406 Example Vector-looped add operation implementation when elwidths are 64-bit:
409 # vector-add RT, RA,RB using the "uint64_t" union member, "dwords"
411 int_regfile[RT].dword[i] = int_regfile[RA].dword[i] + int_regfile[RB].dword[i]
414 However if elwidth overrides are set to 16 for both source and destination:
417 # vector-add RT, RA, RB using the "uint64_t" union member "hwords"
419 int_regfile[RT].hwords[i] = int_regfile[RA].hwords[i] + int_regfile[RB].hwords[i]
422 The most fundamental aspect here to understand is that the wrapping
423 into subsequent Scalar GPRs that occurs on larger-numbered elements
424 including and especially on smaller element widths is **deliberate
425 and intentional**. From this Canonical definition it should be clear
426 that sequential elements begin at the LSB end of any given underlying
427 Scalar GPR, progress to the MSB end, and then to the LSB end of the
428 *next numerically-larger Scalar GPR*. In the example above if VL=5
429 and RT=1 then the contents of GPR(1) and GPR(2) will be as follows.
430 For clarity in the table below:
432 * Both MSB0-ordered bitnumbering *and* LSB-ordered bitnumbering are shown
433 * The GPR-numbering is considered LSB0-ordered
434 * The Element-numbering (result0-result4) is LSB0-ordered
435 * Each of the results (result0-result4) are 16-bit
436 * "same" indicates "no change as a result of the Vectorized add"
439 | MSB0: | 0:15 | 16:31 | 32:47 | 48:63 |
440 | LSB0: | 63:48 | 47:32 | 31:16 | 15:0 |
441 |--------|---------|---------|---------|---------|
442 | GPR(0) | same | same | same | same |
443 | GPR(1) | result3 | result2 | result1 | result0 |
444 | GPR(2) | same | same | same | result4 |
445 | GPR(3) | same | same | same | same |
446 | ... | ... | ... | ... | ... |
447 | ... | ... | ... | ... | ... |
450 Note that the upper 48 bits of GPR(2) would **not** be modified due to
451 the example having VL=5. Thus on "wrapping" - sequential progression
452 from GPR(1) into GPR(2) - the 5th result modifies **only** the bottom
455 If the 16-bit operation were to be followed up with a 32-bit Vectorized
456 Operation, the exact same contents would be viewed as follows:
459 | MSB0: | 0:31 | 32:63 |
460 | LSB0: | 63:32 | 31:0 |
461 |--------|----------------------|----------------------|
462 | GPR(0) | same | same |
463 | GPR(1) | (result3 || result2) | (result1 || result0) |
464 | GPR(2) | same | (same || result4) |
465 | GPR(3) | same | same |
470 In other words, this perspective really is no different from the situation
471 where the actual Register File is treated as an Industry-standard
472 byte-level-addressable Little-Endian-addressed SRAM. Note that
473 this perspective does **not** involve `MSR.LE` in any way shape or
474 form because `MSR.LE` is directly in control of the Memory-to-Register
475 byte-ordering. This section is exclusively about how to correctly perceive
476 Simple-V-Augmented **Register** Files.
478 *Engineering note: to avoid a Read-Modify-Write at the register
479 file it is strongly recommended to implement byte-level write-enable lines
480 exactly as has been implemented in DRAM ICs for many decades. Additionally
481 the predicate mask bit is advised to be associated with the element
482 operation and alongside the result ultimately passed to the register file.
483 When element-width is set to 64-bit the relevant predicate mask bit
484 may be repeated eight times and pull all eight write-port byte-level
485 lines HIGH. Clearly when element-width is set to 8-bit the relevant
486 predicate mask bit corresponds directly with one single byte-level
487 write-enable line. It is up to the Hardware Architect to then amortise
488 (merge) elements together into both PredicatedSIMD Pipelines as well
489 as simultaneous non-overlapping Register File writes, to achieve High
490 Performance designs. Overall it helps to think of the GPR and FPR
491 register files as being much more akin to a 64-bit-wide byte-level-addressable SRAM.*
493 **Comparative equivalent using VSR registers**
495 For a comparative data point the VSR Registers may be expressed in the
496 same fashion. The c code below is directly an expression of Figure 97 in
497 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating
498 for MSB0 numbering in both bits and elements, adapting in full to LSB0
499 numbering, and obeying LE ordering*.
501 **Crucial to understanding why the subtraction from 1,3,7,15 is present is
502 because the Power ISA numbers VSX Registers elements also in MSB0 order**.
503 SVP64 very specifically numbers elements in **LSB0** order with the first
504 element (numbered zero) being at the bitwise-numbered **LSB** end of the
505 register, where VSX does the reverse: places the numerically-*highest*
506 (last-numbered) element at the LSB end of the register.
511 // these do NOT match their Power ISA VSX numbering directly, they are all reversed
512 // bytes[15] is actually VSR.byte[0] for example. if this convention is not
513 // followed then everything ends up in the wrong place
514 uint8_t bytes[16]; // elwidth 8, QTY 16 FIXED total
515 uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total
516 uint32_t words[4]; // elwidth 32, QTY 8 FIXED total
517 uint64_t dwords[2]; // elwidth 64, QTY 2 FIXED total
518 uint8_t actual_bytes[16]; // totals 128-bit
521 elreg_t VSR_regfile[64];
523 static void check_num_elements(int elt, int width) {
525 case 64: assert elt < 2;
526 case 32: assert elt < 4;
527 case 16: assert elt < 8;
528 case 8 : assert elt < 16;
531 void get_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
532 check_num_elements(elt, width);
534 case 64: el->dwords[0] = VSR_regfile[gpr].dwords[1-elt];
535 case 32: el->words[0] = VSR_regfile[gpr].words[3-elt];
536 case 16: el->hwords[0] = VSR_regfile[gpr].hwords[7-elt];
537 case 8 : el->bytes[0] = VSR_regfile[gpr].bytes[15-elt];
540 void set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
541 check_num_elements(elt, width);
543 case 64: VSR_regfile[gpr].dwords[1-elt] = el->dwords[0];
544 case 32: VSR_regfile[gpr].words[3-elt] = el->words[0];
545 case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[0];
546 case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[0];
551 For VSR Registers one key difference is that the overlay of different
552 element widths is clearly a *bounded static quantity*, whereas for
553 Simple-V the elements are unrestrained and permitted to flow into
554 *successive underlying Scalar registers*. This difference is absolutely
555 critical to a full understanding of the entire Simple-V paradigm and
556 why element-ordering, bit-numbering *and register numbering* are all so
559 Implementations are not permitted to violate the Canonical
560 definition. Software will be critically relying on the wrapped (overflow)
561 behaviour inherently implied by the unbounded variable-length c arrays.
563 Illustrating the exact same loop with the exact same effect as achieved
564 by Simple-V we are first forced to create wrapper functions, to cater
565 for the fact that VSR register elements are static bounded:
568 int calc_VSR_reg_offs(int elt, int width) {
570 case 64: return floor(elt / 2);
571 case 32: return floor(elt / 4);
572 case 16: return floor(elt / 8);
573 case 8 : return floor(elt / 16);
576 int calc_VSR_elt_offs(int elt, int width) {
578 case 64: return (elt % 2);
579 case 32: return (elt % 4);
580 case 16: return (elt % 8);
581 case 8 : return (elt % 16);
584 void _set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
585 int new_elt = calc_VSR_elt_offs(elt, width);
586 int new_reg = calc_VSR_reg_offs(elt, width);
587 set_VSR_element(el, gpr+new_reg, new_elt, width);
591 And finally use these functions:
594 # VSX-add RT, RA, RB using the "uint64_t" union member "hwords"
596 el_reg_t result, ra, rb;
597 _get_VSR_element(&ra, RA, i, 16);
598 _get_VSR_element(&rb, RB, i, 16);
599 result.hwords[0] = ra.hwords[0] + rb.hwords[0]; // use array 0 elements
600 _set_VSR_element(&result, RT, i, 16);
604 ## Scalar Identity Behaviour
606 SVP64 is designed so that when the prefix is all zeros, and VL=1, no
607 effect or influence occurs (no augmentation) such that all standard Power
608 ISA v3.0/v3.1 instructions covered by the prefix are "unaltered". This
609 is termed `scalar identity behaviour` (based on the mathematical
610 definition for "identity", as in, "identity matrix" or better "identity
613 Note that this is completely different from when VL=0. VL=0 turns all
614 operations under its influence into `nops` (regardless of the prefix)
615 whereas when VL=1 and the SV prefix is all zeros, the operation simply
616 acts as if SV had not been applied at all to the instruction (an
617 "identity transformation").
619 The fact that `VL` is dynamic and can be set to any value at runtime
620 based on program conditions and behaviour means very specifically that
621 `scalar identity behaviour` is **not** a redundant encoding. If the only
622 means by which VL could be set was by way of static-compiled immediates
623 then this assertion would be false. VL should not be confused with
624 MAXVL when understanding this key aspect of SimpleV.
626 ## Register Naming and size
628 As indicated above SV Registers are simply the GPR, FPR and CR register
629 files extended linearly to larger sizes; SV Vectorization iterates
630 sequentially through these registers (LSB0 sequential ordering from 0
633 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
634 r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV)
635 as r0 to r127. Likewise FP registers are
636 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
637 CR0 thru CR127. In the Lower SV Compliancy Levels the quantity of registers
638 remains the same in order to reduce implementation cost for Embedded systems.
640 The names of the registers therefore reflects a simple linear extension
641 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
642 would be reflected by a linear increase in the size of the underlying
643 SRAM used for the regfiles.
645 Note: when an EXTRA field (defined below) is zero, SV is deliberately
646 designed so that the register fields are identical to as if SV was not in
647 effect i.e. under these circumstances (EXTRA=0) the register field names
648 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
649 This is part of `scalar identity behaviour` described above.
651 **Condition Register(s)**
653 The Scalar Power ISA Condition Register is a 64 bit register where
654 the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used.
655 This convention is *preserved* in SVP64 and an additional 15 Condition
656 Registers provided in order to store the new CR Fields, CR8-CR15,
657 CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition
658 Register are *also* not used: only the bottom 32 bits (numbered 32:63
661 *Programmer's note: using `sv.mfcr` without element-width overrides
662 to take into account the fact that the top 32 MSBs are zero and thus
663 effectively doubling the number of GPR registers required to hold all 128
664 CR Fields would seem the only option because a source elwidth override
665 to 32-bit would take only the bottom 16 LSBs of the Condition Register
666 and set the top 16 LSBs to zeros. However in this case it
667 is possible to use destination element-width overrides (for `sv.mfcr`.
668 source overrides would be used on the GPR of `sv.mtocrf`), whereupon
669 truncation of the 64-bit Condition Register(s) occurs, throwing away
670 the zeros and storing the remaining (valid, desired) 32-bit values
671 sequentially into (LSB0-convention) lower-numbered and upper-numbered
672 halves of GPRs respectively. The programmer is expected to be aware
673 however that the full width of the entire 64-bit Condition Register
674 is considered to be "an element". This is **not** like any other
675 Condition-Register instructions because all other CR instructions,
676 on closer investigation, will be observed to all be CR-bit or CR-Field
677 related. Thus a `VL` of 16 must be used*
679 **Condition Register Fields as Predicate Masks**
681 Condition Register Fields perform an additional duty in Simple-V: they are
682 used for Predicate Masks. ARM's Scalar Instruction Set calls single-bit
683 predication "Conditional Execution", and utilises Condition Codes for
684 exactly this purpose to solve the problem caused by Branch Speculation.
685 In a Vector ISA context the concept of Predication is naturally extended
686 from single-bit to multi-bit, and the (well-known) benefits become all the
687 more critical given that parallel branches in Vector ISAs are impossible
688 (even a Vector ISA can only have Scalar branches).
690 However the Scalar Power ISA does not have Conditional Execution (for
691 which, if it had ever been considered, Condition Register bits would be
692 a perfect natural fit). Thus, when adding Predication using CR Fields
693 via Simple-V it becomes a somewhat disruptive addition to the Power ISA.
695 To ameliorate this situation, particularly for pre-existing Hardware
696 designs implementing up to Scalar Power ISA v3.1, some rules are set that
697 allow those pre-existing designs not to require heavy modification to
698 their existing Scalar pipelines. These rules effectively allow Hardware
699 Architects to add the additional CR Fields CR8 to CR127 as if they were
700 an **entirely separate register file**.
702 * any instruction involving more than 1 source 1 destination
703 where one of the operands is a Condition Register is prohibited from
704 using registers from both the CR0-7 group and the CR8-127 group at
706 * any instruction involving 1 source 1 destination where either the
707 source or the destination is a Condition Register is prohibited
708 from setting CR0-7 as a Vector.
709 * prohibitions are required to be enforced by raising Illegal Instruction
712 Examples of permitted instructions:
715 sv.crand *cr8.eq, *cr16.le, *cr40.so # all CR8-CR127
716 sv.mfcr cr5, *cr40 # only one source (CR40) copied to CR5
717 sv.mfcr *cr16, cr40 # Vector-Splat CR40 onto CR16,17,18...
718 sv.mfcr *cr16, cr3 # Vector-Splat CR3 onto CR16,17,18...
721 Examples of prohibited instructions:
724 sv.mfcr *cr0, cr40 # Vector-Splat onto CR0,1,2
725 sv.crand cr7, cr9, cr10 # crosses over between CR0-7 and CR8-127
730 With the way that EXTRA fields are defined and applied to register
731 fields, future versions of SV may involve 256 or greater registers
732 in some way as long as the reputation of Power ISA for full backwards
733 binary interoperability is preserved. Backwards binary compatibility
734 may be achieved with a PCR bit (Program Compatibility Register) or an
735 MSR bit analogous to SF. Further discussion is out of scope for this
738 Additionally, a future variant of SVP64 will be applied to the Scalar
739 (Quad-precision and 128-bit) VSX instructions. Element-width overrides are
740 an opportunity to expand a future version of the Power ISA to 256-bit,
741 512-bit and 1024-bit operations, as well as doubling or quadrupling the
742 number of VSX registers to 128 or 256. Again further discussion is out
743 of scope for this version of SVP64.
749 ## SVP64 Remapped Encoding (`RM[0:23]`)
751 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits
752 32-37 are the Primary Opcode of the Suffix "Defined Word-instruction". 38-63 are the
753 remainder of the Defined Word-instruction. Note that the new EXT232-263 SVP64 area
754 it is obviously mandatory that bit 32 is required to be set to 1.
756 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
757 |-----|---|---|----------|--------|----------|-----------------------|
758 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
759 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
761 It is important to note that unlike EXT1xx 64-bit prefixed instructions
762 there is insufficient space in `RM` to provide identification of
763 any SVP64 Fields without first partially decoding the 32-bit suffix.
764 Similar to the "Forms" (X-Form, D-Form) the `RM` format is individually
765 associated with every instruction. However this still does not adversely
766 affect Multi-Issue Decoding because the identification of the *length*
767 of anything in the 64-bit space has been kept brutally simple (EXT009),
768 and further decoding of any number of 64-bit Encodings in parallel at
769 that point is fully independent.
771 Extreme caution and care must be taken when extending SVP64
772 in future, to not create unnecessary relationships between prefix and
773 suffix that could complicate decoding, adding latency.
777 The following fields are common to all Remapped Encodings:
779 | Field Name | Field bits | Description |
780 |------------|------------|----------------------------------------|
781 | MASKMODE | `0` | Execution (predication) Mask Kind |
782 | MASK | `1:3` | Execution Mask |
783 | SUBVL | `8:9` | Sub-vector length |
785 The following fields are optional or encoded differently depending
786 on context after decoding of the Scalar suffix:
788 | Field Name | Field bits | Description |
789 |------------|------------|----------------------------------------|
790 | ELWIDTH | `4:5` | Element Width |
791 | ELWIDTH_SRC | `6:7` | Element Width for Source (or MASK_SRC in 2PM) |
792 | EXTRA | `10:18` | Register Extra encoding |
793 | MODE | `19:23` | changes Vector behaviour |
795 * MODE changes the behaviour of the SV operation (result saturation,
797 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
798 and Audio/Video DSP work
799 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
801 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
802 sources: scalar INT and Vector CR).
803 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
804 for the instruction, which is determined only by decoding the Scalar 32
807 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
808 such as `RM-1P-3S1D` which indicates for this example that the operation
809 is to be single-predicated and that there are 3 source operand EXTRA
810 tags and one destination operand tag.
812 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
813 or increased latency in some implementations due to lane-crossing.
817 Mode is an augmentation of SV behaviour. Different types of instructions
818 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
819 formats apply to different instruction types. Modes include Reduction,
820 Iteration, arithmetic saturation, and Fail-First. More specific details
821 in each section and in the [[svp64/appendix]]
823 * For condition register operations see [[sv/cr_ops]]
824 * For LD/ST Modes, see [[sv/ldst]].
825 * For Branch modes, see [[sv/branches]]
826 * For arithmetic and logical, see [[sv/normal]]
830 Default behaviour is set to 0b00 so that zeros follow the convention
831 of `scalar identity behaviour`. In this case it means that elwidth
832 overrides are not applicable. Thus if a 32 bit instruction operates
833 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
834 Likewise when a processor is switched from 64 bit to 32 bit mode,
835 `elwidth=0b00` states that, again, the behaviour is not to be modified.
837 Only when elwidth is nonzero is the element width overridden to the
838 explicitly required value.
840 ### Elwidth for Integers:
842 | Value | Mnemonic | Description |
843 |-------|----------------|------------------------------------|
844 | 00 | DEFAULT | default behaviour for operation |
845 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
846 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
847 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
849 This encoding is chosen such that the byte width may be computed as
852 ### Elwidth for FP Registers:
854 | Value | Mnemonic | Description |
855 |-------|----------------|------------------------------------|
856 | 00 | DEFAULT | default behaviour for FP operation |
857 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
858 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
859 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
862 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
863 is reserved for a future implementation of SV
865 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`)
866 shall perform its operation at **half** the ELWIDTH then padded back out
867 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation
868 that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
869 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
870 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
871 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16 or
872 ELWIDTH=bf16 is reserved and must raise an illegal instruction (IEEE754
873 FP8 or BF8 are not defined).
875 ### Elwidth for CRs (no meaning)
877 Element-width overrides for CR Fields has no meaning. The bits
878 are therefore used for other purposes, or when Rc=1, the Elwidth
879 applies to the result being tested (a GPR or FPR), but not to the
884 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
885 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
886 lines up in combination with all other "default is all zeros" behaviour.
888 | Value | Mnemonic | Subvec | Description |
889 |-------|-----------|---------|------------------------|
890 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
891 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
892 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
893 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
895 The SUBVL encoding value may be thought of as an inclusive range of a
896 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
897 this may be considered to be elements 0b00 to 0b01 inclusive.
899 Effectively, SUBVL is like a SIMD multiplier: instead of just 1
900 element operation issued, SUBVL element operations are issued (as an inner loop).
901 The key difference between VL looping and SUBVL looping
902 is that predication bits are applied per
903 **group**, rather than by individual element.
905 Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
907 ## MASK/MASK_SRC & MASKMODE Encoding
909 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
910 types may not be mixed.
912 Special note: to disable predication this field must be set to zero in
913 combination with Integer Predication also being set to 0b000. this has the
914 effect of enabling "all 1s" in the predicate mask, which is equivalent to
915 "not having any predication at all".
917 `MASKMODE` may be set to one of 2 values:
919 | Value | Description |
920 |-----------|------------------------------------------------------|
921 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
922 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
924 Integer Twin predication has a second set of 3 bits that uses the same
925 encoding thus allowing either the same register (r3, r10 or r31) to be
926 used for both src and dest, or different regs (one for src, one for dest).
928 Likewise CR based twin predication has a second set of 3 bits, allowing
929 a different test to be applied.
931 Note that it cannot necessarily be assumed that Predicate Masks
932 (whether INT or CR) are read in full *before* the operations proceed. In practice (for CR Fields)
933 this creates an unnecessary block on parallelism, prohibiting
934 "Vector Chaining". Therefore, it is up
935 to the programmer to ensure that the CR field Elements used as Predicate Masks
936 are not overwritten by any parallel Vector Loop. Doing so results
937 in **UNDEFINED** behaviour, according to the definition outlined in the
938 Power ISA v3.0B Specification.
940 Hardware Implementations are therefore free and clear to delay reading
941 of individual CR fields until the actual predicated element operation
942 needs to take place, safe in the knowledge that no programmer will have
943 issued a Vector Instruction where previous elements could have overwritten
944 (destroyed) not-yet-executed CR-Predicated element operations.
945 This particularly is an issue when using REMAP, as the order in
946 which CR-Field-based Predicate Mask bits could be read on a per-element
947 execution basis could well conflict with the order in which prior
948 elements wrote to the very same CR Field.
950 Additionally Programmers should avoid using r3 r10 or r30
951 as destination registers when these are also used as a Predicate
952 Mask. Doing so is again UNDEFINED behaviour.
954 Usually in 2P `MASK_SRC` is exclusively in the EXTRA area. However for
955 LD/ST-Indexed a different Encoding is required, designated `2PM`.
957 ### Integer Predication (MASKMODE=0)
959 When the predicate mode bit is zero the 3 bits are interpreted as below.
960 Twin predication has an identical 3 bit field similarly encoded.
962 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
965 | Value | Mnemonic | Element `i` enabled if: |
966 |-------|----------|------------------------------|
967 | 000 | ALWAYS | predicate effectively all 1s |
968 | 001 | 1 << R3 | `i == R3` |
969 | 010 | R3 | `R3 & (1 << i)` is non-zero |
970 | 011 | ~R3 | `R3 & (1 << i)` is zero |
971 | 100 | R10 | `R10 & (1 << i)` is non-zero |
972 | 101 | ~R10 | `R10 & (1 << i)` is zero |
973 | 110 | R30 | `R30 & (1 << i)` is non-zero |
974 | 111 | ~R30 | `R30 & (1 << i)` is zero |
976 r10 and r30 are at the high end of temporary and unused registers,
977 so as not to interfere with register allocation from ABIs.
979 ### CR-based Predication (MASKMODE=1)
981 When the predicate mode bit is one the 3 bits are interpreted as below.
982 Twin predication has an identical 3 bit field similarly encoded.
984 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
987 | Value | Mnemonic | Element `i` is enabled if |
988 |-------|----------|--------------------------|
989 | 000 | lt | `CR[offs+i].LT` is set |
990 | 001 | nl/ge | `CR[offs+i].LT` is clear |
991 | 010 | gt | `CR[offs+i].GT` is set |
992 | 011 | ng/le | `CR[offs+i].GT` is clear |
993 | 100 | eq | `CR[offs+i].EQ` is set |
994 | 101 | ne | `CR[offs+i].EQ` is clear |
995 | 110 | so/un | `CR[offs+i].FU` is set |
996 | 111 | ns/nu | `CR[offs+i].FU` is clear |
998 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorized
999 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
1001 The CR Predicates chosen must start on a boundary that Vectorized CR
1002 operations can access cleanly, in full. With EXTRA2 restricting starting
1003 points to multiples of 8 (CR0, CR8, CR16...) both Vectorized Rc=1 and
1004 CR Predicate Masks have to be adapted to fit on these boundaries as well.
1006 ## Extra Remapped Encoding <a name="extra_remap"> </a>
1008 Shows all instruction-specific fields in the Remapped Encoding
1009 `RM[10:18]` for all instruction variants. Note that due to the very
1010 tight space, the encoding mode is *not* included in the prefix itself.
1011 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
1012 on a per-instruction basis, and, like "Forms" are given a designation
1013 (below) of the form `RM-nP-nSnD`. The full list of which instructions
1014 use which remaps is here [[opcode_regs_deduped]].
1016 **Please note the following**:
1019 Machine-readable CSV files have been autogenerated which will make the
1020 task of creating SV-aware ISA decoders, documentation, assembler tools
1021 compiler tools Simulators documentation all aspects of SVP64 easier
1022 and less prone to mistakes. Please avoid manual re-creation of
1023 information from the written specification wording in this chapter,
1024 and use the CSV files or use the Canonical tool which creates the CSV
1025 files, named sv_analysis.py. The information contained within
1026 sv_analysis.py is considered to be part of this Specification, even
1027 encoded as it is in python3.
1031 The mappings are part of the SVP64 Specification in exactly the same
1032 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
1033 will need a corresponding SVP64 Mapping, which can be derived by-rote
1034 from examining the Register "Profile" of the instruction.
1036 There are two categories: Single and Twin Predication. Due to space
1037 considerations further subdivision of Single Predication is based on
1038 whether the number of src operands is 2 or 3. With only 9 bits available
1039 some compromises have to be made.
1041 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
1042 instructions (fmadd, isel, madd).
1043 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
1044 instructions (src1 src2 dest)
1045 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
1046 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
1047 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
1048 * `RM-2PM-2S1D` Twin Predication (src=2, dest=1) for LD/ST Update (Indexed)
1050 The `2PM` designation uses bits 6 and 7 as well as the 9 EXTRA bits
1051 in order to extend two registers to
1052 EXTRA3, sacrificing destination elwidths in the process.
1053 `MASK_SRC` has a different encoding in `2PM`.
1057 | Field Name | Field bits | Description |
1058 |------------|------------|----------------------------------------|
1059 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1060 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1061 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1062 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1063 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
1065 These are for 3 operand in and either 1 or 2 out instructions.
1066 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
1067 such as `maddedu` have an implicit second destination, RS, the
1068 selection of which is determined by bit 18.
1072 | Field Name | Field bits | Description |
1073 |------------|------------|-------------------------------------------|
1074 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
1075 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
1076 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
1078 These are for 2 operand 1 dest instructions, such as `add RT, RA,
1079 RB`. However also included are unusual instructions with an implicit
1080 dest that is identical to its src reg, such as `rlwinmi`.
1082 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
1083 not have sufficient bit fields to allow an alternative destination.
1084 With SV however this becomes possible. Therefore, the fact that the
1085 dest is implicitly also a src should not mislead: due to the *prefix*
1086 they are different SV regs.
1088 * `rlwimi RA, RS, ...`
1089 * Rsrc1_EXTRA3 applies to RS as the first src
1090 * Rsrc2_EXTRA3 applies to RA as the second src
1091 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
1093 With the addition of the EXTRA bits, the three registers
1094 each may be *independently* made vector or scalar, and be independently
1095 augmented to 7 bits in length.
1099 | Field Name | Field bits | Description |
1100 |------------|------------|----------------------------|
1101 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1102 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1103 | MASK_SRC | `16:18` | Execution Mask for Source |
1105 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
1107 | Field Name | Field bits | Description |
1108 |------------|------------|----------------------------|
1109 | Rsrc1_EXTRA3 | `10:12` | extends Rsrc1 |
1110 | Rsrc2_EXTRA3 | `13:15` | extends Rsrc2 |
1111 | MASK_SRC | `16:18` | Execution Mask for Source |
1115 single-predicate, three registers (2 read, 1 write)
1117 | Field Name | Field bits | Description |
1118 |------------|------------|----------------------------|
1119 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1120 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1121 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
1123 ### RM-2P-2S1D/1S2D/3S
1125 The primary purpose for this encoding is for Twin Predication on LOAD
1126 and STORE operations. see [[sv/ldst]] for detailed analysis.
1130 | Field Name | Field bits | Description |
1131 |------------|------------|----------------------------|
1132 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1133 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1134 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1135 | MASK_SRC | `16:18` | Execution Mask for Source |
1139 For RM-2P-1S2D dest2 is in bits 14:15
1141 | Field Name | Field bits | Description |
1142 |------------|------------|----------------------------|
1143 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1144 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1145 | Rdest2_EXTRA2 | `14:15` | extends Rdest22 (R\*\_EXTRA2 Encoding) |
1146 | MASK_SRC | `16:18` | Execution Mask for Source |
1150 Also that for RM-2P-3S (to cover `stdx` etc.) the names are switched to 3 src:
1151 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
1153 | Field Name | Field bits | Description |
1154 |------------|------------|----------------------------|
1155 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1156 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1157 | Rsrc3_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1158 | MASK_SRC | `16:18` | Execution Mask for Source |
1160 Note also that LD with update indexed, which takes 2 src and
1161 creates 2 dest registers (e.g. `lhaux RT,RA,RB`), does not have room
1162 for 4 registers and also Twin Predication. Therefore these are treated as
1163 RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest.
1165 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
1166 or increased latency in some implementations due to lane-crossing.
1168 ### RM-2PM-2S1D/1S2D/3S
1170 The primary purpose for this encoding is for Twin Predication on LOAD
1171 and STORE operations providing EXTRA3 for RT, RA and RS.
1172 see [[sv/ldst]] for detailed analysis.
1176 RT or RS requires EXTRA3, RA requires EXTRA3, but for RB EXTRA2 will
1177 suffice. `MASK_SRC` may be read from the bits normally used for dest-elwidth.
1179 | Field Name | Field bits | Description |
1180 |------------|------------|----------------------------|
1181 | Rdest_EXTRA3 | `10:12` | extends Rdest (R\*\_EXTRA2 Encoding) |
1182 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1183 | Rsrc2_EXTRA2 | `16:17` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1184 | MASK_SRC | `6:7,18` | Execution Mask for Source |
1188 EXTRA is the means by which two things are achieved:
1190 1. Registers are marked as either Vector *or Scalar*
1191 2. Register field numbers (limited typically to 5 bit)
1192 are extended in range, both for Scalar and Vector.
1194 The register files are therefore extended:
1196 * INT (GPR) is extended from r0-31 to r0-127
1197 * FP (FPR) is extended from fp0-32 to fp0-fp127
1198 * CR Fields are extended from CR0-7 to CR0-127
1200 However due to pressure in `RM.EXTRA` not all these registers
1201 are accessible by all instructions, particularly those with
1202 a large number of operands (`madd`, `isel`).
1204 In the following tables register numbers are constructed from the
1205 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
1206 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
1207 designation for a given instruction. The prefixing is arranged so that
1208 interoperability between prefixing and nonprefixing of scalar registers
1209 is direct and convenient (when the EXTRA field is all zeros).
1211 A pseudocode algorithm explains the relationship, for INT/FP (see
1212 [[svp64/appendix]] for CRs)
1218 spec = EXTRA2 << 1 # same as EXTRA3, shifted
1219 if spec[0]: # vector
1220 return (RA << 2) | spec[1:2]
1222 return (spec[1:2] << 5) | RA
1225 Future versions may extend to 256 by shifting Vector numbering up.
1226 Scalar will not be altered.
1228 Note that in some cases the range of starting points for Vectors
1233 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
1236 Fields are as follows:
1239 * Mode: register is tagged as scalar or vector
1240 * Range/Inc: the range of registers accessible from this EXTRA
1241 encoding, and the "increment" (accessibility). "/4" means
1242 that this EXTRA encoding may only give access (starting point)
1244 * MSB..LSB: the bit field showing how the register opcode field
1245 combines with EXTRA to give (extend) the register number (GPR)
1247 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1249 | Value | Mode | Range/Inc | 6..0 |
1250 |-----------|-------|---------------|---------------------|
1251 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
1252 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
1253 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
1254 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
1255 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
1256 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
1257 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
1258 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
1262 If EXTRA2 is zero will map to "scalar identity behaviour" i.e Scalar
1263 Power ISA register naming:
1265 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1267 | Value | Mode | Range/inc | 6..0 |
1268 |----------|-------|---------------|-----------|
1269 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
1270 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
1271 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
1272 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
1274 **Note that unlike in EXTRA3, in EXTRA2**:
1276 * the GPR Vectors may only start from
1277 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
1278 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
1280 as there is insufficient bits to cover the full range.
1284 CR Field encoding is essentially the same but made more complex due to CRs
1285 being bit-based, because the application of SVP64 element-numbering applies
1286 to the CR *Field* numbering not the CR register *bit* numbering.
1287 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
1288 and Scalars may only go from `CR0, CR1, ... CR31`
1290 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1291 BA ranges are in MSB0.
1293 For a 5-bit operand (BA, BB, BT):
1295 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1296 |-------|------|---------------|-----------| --------|---------|
1297 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1298 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1299 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
1300 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
1301 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1302 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
1303 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1304 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
1306 For a 3-bit operand (e.g. BFA):
1308 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1309 |-------|------|---------------|-----------| --------|
1310 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1311 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1312 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
1313 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
1314 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1315 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
1316 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1317 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
1321 CR encoding is essentially the same but made more complex due to CRs
1322 being bit-based, because the application of SVP64 element-numbering applies
1323 to the CR *Field* numbering not the CR register *bit* numbering.
1324 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
1326 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1327 BA ranges are in MSB0.
1329 For a 5-bit operand (BA, BB, BC):
1331 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1332 |-------|--------|----------------|---------|---------|---------|
1333 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1334 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1335 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1336 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1338 For a 3-bit operand (e.g. BFA):
1340 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1341 |-------|------|---------------|-----------| --------|
1342 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1343 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1344 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1345 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1350 Now at its own page: [[svp64/appendix]]