openpower/sv/svp64.mdwn

   1 # SVP64 for OpenPower ISA v3.0B
   2
   3 [[!toc]]
   4
   5 # Links
   6
   7 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
   8 * [[svp64/discussion]]
   9 * [[svp64/appendix]]
  10 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
  11 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
  12
  13 # Introduction
  14
  15 This document focuses on the encoding of [[SV|sv]].  It it best read in conjunction with the [[sv/overview]] which explains the background.
  16
  17 The plan is to create an encoding for SVP64, then to create an encoding
  18 for SVP48, then to reorganize them both to improve field overlap,
  19 reducing the amount of decoder hardware necessary.
  20
  21 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
  22 and counting up as you move to the LSB end). All bit ranges are inclusive
  23 (so `4:6` means bits 4, 5, and 6).
  24
  25 64-bit instructions are split into two 32-bit words, the prefix and the
  26 suffix. The prefix always comes before the suffix in PC order.
  27
  28 | 0:5    | 6:31         | 0:31         |
  29 |--------|--------------|--------------|
  30 | EXT01  | v3.1B Prefix | v3.1B Suffix |
  31
  32 svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions  to co-exist in the same binary without conflict.
  33
  34 # Definition of Reserved in this spec.
  35
  36 For the new fields added in SVP64, instructions that have any of their
  37 fields set to a reserved value must cause an illegal instruction trap,
  38 to allow emulation of future instruction sets.
  39
  40 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
  41
  42 # Identity Behaviour
  43
  44 SVP64 is designed so that when the prefix is all zeros, and
  45  VL=1, no effect or
  46 influence occurs (no augmentation) such that all standard OpenPOWER
  47 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
  48
  49 Note that this is completely different from when VL=0.  VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
  50  whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction  (an "identity operation").
  51
  52 # Register Naming and size
  53
  54 SV Registers are simply the INT, FP and CR register files extended
  55 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
  56
  57 Where the integer regfile in standard scalar
  58 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
  59 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
  60 extended to 64 entries, CR0 thru CR63.
  61
  62 The names of the registers therefore reflects a simple linear extension
  63 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
  64 would be reflected by a linear increase in the size of the underlying
  65 SRAM used for the regfiles.
  66
  67 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
  68 so that the register fields are identical to as if SV was not in effect
  69 i.e. under these circumstances (EXTRA=0) the register field names RA,
  70 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.  This is part of
  71 `scalar identity behaviour` described above.
  72
  73 ## Future expansion.
  74
  75 With the way that EXTRA fields are defined and applied to register fields,
  76 future versions of SV may involve 256 or greater registers.  To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
  77 requiring additional prefix bits.  Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register).  Beyond this, further discussion is out of scope for this version of svp64.
  78
  79 # Remapped Encoding (`RM[0:23]`)
  80
  81 To allow relatively easy remapping of which portions of the Prefix Opcode
  82 Map are used for SVP64 without needing to rewrite a large portion of the
  83 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
  84 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
  85 at the LSB.
  86
  87 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
  88 is defined in the Prefix Fields section.
  89
  90 ## Prefix Opcode Map (64-bit instruction encoding)
  91
  92 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
  93
  94 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
  95 empty spaces are yet-to-be-allocated Illegal Instructions.
  96
  97 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
  98 |------|--------|--------|--------|--------|--------|--------|--------|--------|
  99 |000---| 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    |
 100 |001---|        |        |        |        |        |        |        |        |
 101 |010---| 8RR    |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 102 |011---|        |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 103 |100---| MLS    | MLS    | MLS    | MLS    | MLS    | MLS    | MLS    | MLS    |
 104 |101---|        |        |        |        |        |        |        |        |
 105 |110---| MRR    |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 106 |111---|        | MMIRR  |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 107
 108 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
 109
 110 ## Prefix Fields
 111
 112 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
 113 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
 114 This is achieved by setting bits 7 and 9 to 1:
 115
 116 | Name       | Bits    | Value | Description                    |
 117 |------------|---------|-------|--------------------------------|
 118 | EXT01      | `0:5`   | `1`   | Indicates Prefixed 64-bit      |
 119 | `RM[0]`    | `6`     |       | Bit 0 of Remapped Encoding     |
 120 | SVP64_7    | `7`     | `1`   | Indicates this is SVP64        |
 121 | `RM[1]`    | `8`     |       | Bit 1 of Remapped Encoding     |
 122 | SVP64_9    | `9`     | `1`   | Indicates this is SVP64        |
 123 | `RM[2:23]` | `10:31` |       | Bits 2-23 of Remapped Encoding |
 124
 125 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
 126 are constructed:
 127
 128 | 0:5    | 6     | 7 | 8     | 9 | 10:31    |
 129 |--------|-------|---|-------|---|----------|
 130 | EXT01  | RM    | 1 | RM    | 1 | RM       |
 131 | 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
 132
 133 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
 134 instruction.  That instruction becomes "prefixed" with the SVP context: the
 135 Remapped Encoding field (RM).
 136
 137 # Remapped Encoding Fields
 138
 139 Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
 140 variants.  There are two categories:  Single and Twin Predication.
 141 Due to space considerations further subdivision of Single Predication
 142 is based on whether the number of src operands is 2 or 3.
 143
 144 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
 145 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
 146 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
 147 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
 148 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
 149
 150 ## Common RM fields
 151
 152 The following fields are common to all Remapped Encodings:
 153
 154
 155 | Field Name | Field bits | Description                            |
 156 |------------|------------|----------------------------------------|
 157 | MASK\_KIND    | `0`        | Execution (predication) Mask Kind                 |
 158 | MASK          | `1:3`      | Execution Mask                      |
 159 | ELWIDTH       | `4:5`      | Element Width                       |
 160 | SUBVL         | `6:7`      | Sub-vector length                   |
 161 | MODE          | `19:23` | changes Vector behaviour               |
 162
 163 Bits 9 to 18 are further decoded depending on RM category for the instruction.
 164
 165 ## RM-1P-3S1D
 166
 167 | Field Name | Field bits | Description                            |
 168 |------------|------------|----------------------------------------|
 169 | Rdest\_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 170 | Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 171 | Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 172 | Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding)   |
 173 | reserved      | `16`    | reserved                               |
 174
 175 ## RM-1P-2S1D
 176
 177 | Field Name | Field bits | Description                               |
 178 |------------|------------|-------------------------------------------|
 179 | Rdest\_EXTRA3 | `8:10`  | extends Rdest  |
 180 | Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1  |
 181 | Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3    |
 182 | ELWIDTH_SRC   | `17:18` | Element Width for Source      |
 183
 184 These are for 2 operand 1 dest instructions, such as `add RT, RA,
 185 RB`. However also included are unusual instructions with an implicit dest
 186 that is identical to its src reg, such as `rlwinmi`.
 187
 188 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
 189 an alternative destination.  With SV however this becomes possible.
 190 Therefore, the fact that the dest is implicitly also a src should not
 191 mislead: due to the *prefix* they are different SV regs.
 192
 193 * `rlwimi RA, RS, ...`
 194 * Rsrc1_EXTRA3 applies to RS as the first src
 195 * Rsrc2_EXTRA3 applies to RA as the secomd src
 196 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
 197
 198 With the addition of the EXTRA bits, the three registers
 199 each may be *independently* made vector or scalar, and be independently
 200 augmented to 7 bits in length.
 201
 202 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 203
 204 ## RM-2P-1S1D/2S
 205
 206 | Field Name | Field bits | Description                 |
 207 |------------|------------|----------------------------|
 208 | Rdest_EXTRA3 | `8:10`     | extends Rdest             |
 209 | Rsrc1_EXTRA3 | `11:13`    | extends Rsrc1             |
 210 | MASK_SRC     | `14:16`    | Execution Mask for Source |
 211 | ELWIDTH_SRC  | `17:18`    | Element Width for Source  |
 212
 213 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 214
 215 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 216
 217 ## RM-2P-2S1D/1S2D/3S
 218
 219 The primary purpose for this encoding is for Twin Predication on LOAD
 220 and STORE operations.  see [[sv/ldst]] for detailed anslysis.
 221
 222 RM-2P-2S1D:
 223
 224 | Field Name | Field bits | Description                     |
 225 |------------|------------|----------------------------|
 226 | Rdest_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 227 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 228 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 229 | MASK_SRC     | `14:16`    | Execution Mask for Source     |
 230 | ELWIDTH_SRC  | `17:18`    | Element Width for Source      |
 231
 232 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
 233 is in bits 8:9, Rdest1_EXTRA2 in 10:11)
 234
 235 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
 236
 237 Note also that LD with update indexed, which takes 2 src and 2 dest
 238 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
 239 Twin Predication.  therefore these are treated as RM-2P-2S1D and the
 240 src spec for RA is also used for the same RA as a dest.
 241
 242 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 243
 244 # Mode
 245
 246 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 247
 248 These are the modes:
 249
 250 * **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
 251 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.
 252   *VL is altered as a result*.
 253 * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
 254 * **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see separate section below.
 255   note that there are comprehensive caveats when using this mode.
 256 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  This scheme does not apply to crops (crand, cror).  See appendix for details.
 257
 258 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL.
 259
 260 The Mode table is laid out as follows:
 261
 262 | 0-1 |  2  |  3   4  |  description              |
 263 | --- | --- |---------|-------------------------- |
 264 | 00  |   0 |  sz  dz | normal mode                      |
 265 | 00  |   1 | sz CRM  | reduce mode (mapreduce), SUBVL=1 |
 266 | 00  |   1 | SVM CRM | subvector reduce mode, SUBVL>1   |
 267 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 268 | 01  | inv | sz  RC1 |  Rc=0: ffirst z/nonz |
 269 | 10  |   N | sz   dz |  sat mode: N=0/1 u/s |
 270 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 271 | 11  | inv | sz  RC1 |  Rc=0: pred-result z/nonz |
 272
 273 Fields:
 274
 275 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
 276 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 277 * **CRM** affects the CR on reduce mode when Rc=1
 278 * **SVM** sets "subvector" reduce mode
 279 * **N** sets signed/unsigned saturation.
 280 **RC1** as if Rc=1, stores CRs *but not the result*
 281
 282 # R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
 283
 284 EXTRA is the means by which two things are achieved:
 285
 286 1. Registers are marked as either Vector *or Scalar*
 287 2. Register field numbers (limited typically to 5 bit)
 288    are extended in range, both for Scalar and Vector.
 289
 290 In the following tables register numbers are constructed from the
 291 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
 292 or EXTRA3 field from the SV Prefix.  The prefixing is arranged so that
 293 interoperability between prefixing and nonprefixing of scalar registers
 294 is direct and convenient (when the EXTRA field is all zeros).
 295
 296 A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
 297
 298     if extra3_mode:
 299         spec = EXTRA3
 300     else:
 301         spec = EXTRA2 << 1 # same as EXTRA3, shifted
 302     if spec[2]: # vector
 303          return (RA << 2) | spec[0:1]
 304     else:         # scalar
 305          return (spec[0:1] << 5) | RA
 306
 307 ## INT/FP EXTRA3
 308
 309 alternative which is understandable and, if EXTRA3 is zero, maps to
 310 "no effect" (scalar OpenPOWER ISA field naming).  also, these are the
 311 encodings used in the original SV Prefix scheme.  the reason why they
 312 were chosen is so that scalar registers in v3.0B and prefixed scalar
 313 registers have access to the same 32 registers.
 314
 315 | R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
 316 |-----------|-------|---------------|---------------------|
 317 | 000       | Scalar | `r0-r31` | `0b00 RA`      |
 318 | 001       | Scalar | `r32-r63` | `0b01 RA`      |
 319 | 010       | Scalar | `r64-r95` | `0b10 RA`      |
 320 | 011       | Scalar | `r96-r127` | `0b11 RA`      |
 321 | 100       | Vector | `r0-r124` | `RA 0b00`      |
 322 | 101       | Vector | `r1-r125` | `RA 0b01`      |
 323 | 110       | Vector | `r2-r126` | `RA 0b10`      |
 324 | 111       | Vector | `r3-r127` | `RA 0b11`      |
 325
 326 ## INT/FP EXTRA2
 327
 328 alternative which is understandable and, if EXTRA2 is zero will map to
 329 "no effect" i.e Scalar OpenPOWER register naming:
 330
 331 | R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
 332 |-----------|-------|---------------|---------------------|
 333 | 00       | Scalar | `r0-r31` | `0b00 RA`                |
 334 | 01       | Scalar | `r32-r63` | `0b01 RA`      |
 335 | 10       | Vector | `r0-r124` | `RA 0b00`      |
 336 | 11       | Vector | `r2-r126` | `RA 0b10`   |
 337
 338 ## CR EXTRA3
 339
 340 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
 341
 342  Encoding shown MSB down to LSB
 343
 344 | R\*\_EXTRA3 | Mode | 7..5    | 4..2    | 1..0    |
 345 |-------------|------|---------| --------|---------|
 346 | 000       | Scalar | 0b000   | BA[4:2] | BA[1:0] |
 347 | 001       | Scalar | 0b001   | BA[4:2] | BA[1:0] |
 348 | 010       | Scalar | 0b010   | BA[4:2] | BA[1:0] |
 349 | 011       | Scalar | 0b011   | BA[4:2] | BA[1:0] |
 350 | 100       | Vector | BA[4:2] | 0b000   | BA[1:0] |
 351 | 101       | Vector | BA[4:2] | 0b010   | BA[1:0] |
 352 | 110       | Vector | BA[4:2] | 0b100   | BA[1:0] |
 353 | 111       | Vector | BA[4:2] | 0b110   | BA[1:0] |
 354
 355 ## CR EXTRA2
 356
 357 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
 358
 359 Encoding shown MSB down to LSB
 360
 361 | R\*\_EXTRA2 | Mode   | 7..5    | 4..2    | 1..0    |
 362 |-------------|--------|---------|---------|---------|
 363 | 00          | Scalar | 0b000   | BA[4:2] | BA[1:0] |
 364 | 01          | Scalar | 0b001   | BA[4:2] | BA[1:0] |
 365 | 10          | Vector | BA[4:2] | 0b000   | BA[1:0] |
 366 | 11          | Vector | BA[4:2] | 0b100   | BA[1:0] |
 367
 368 # ELWIDTH Encoding
 369
 370 Default behaviour is set to 0b00 so that zeros follow the convention of
 371 "npt doing anything".  In this case it means that elwidth overrides
 372 are not applicable.  Thus if a 32 bit instruction operates on 32 bit,
 373 `elwidth=0b00` specifies that this behaviour is unmodified.  Likewise
 374 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
 375 states that, again, the behaviour is not to be modified.
 376
 377 Only when elwidth is nonzero is the element width overridden to the
 378 explicitly required value.
 379
 380 ## Elwidth for Integers:
 381
 382 | Value | Mnemonic       | Description                        |
 383 |-------|----------------|------------------------------------|
 384 | 00    | DEFAULT        | default behaviour for operation    |
 385 | 01    | `ELWIDTH=b`    | Byte: 8-bit integer                  |
 386 | 10    | `ELWIDTH=h`    | Halfword: 16-bit integer             |
 387 | 11    | `ELWIDTH=w`    | Word: 32-bit integer                 |
 388
 389 ## Elwidth for FP Registers:
 390
 391 | Value | Mnemonic       | Description                        |
 392 |-------|----------------|------------------------------------|
 393 | 00    | DEFAULT        | default behaviour for FP operation     |
 394 | 01    | `ELWIDTH=bf16` | Reserved for `bf16` |
 395 | 10    | `ELWIDTH=f16`  | 16-bit IEEE 754 Half floating-point   |
 396 | 11    | `ELWIDTH=f32`  | 32-bit IEEE 754 Single floating-point  |
 397
 398 Note:
 399 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
 400 is reserved for a future implementation of SV
 401
 402 ## Elwidth for CRs:
 403
 404 TODO, important, particularly for crops, mfcr and mtcr, what elwidth
 405 even means.  instead it may be possible to use the bits as extra indices
 406 (EXTRA6) to access the full 64 CRs.  TBD, several ideas
 407
 408 The actual width of the CRs cannot be altered: they are 4 bit.  Also,
 409 for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
 410 the INT/FP result to which the elwidth override applies, *not* the CR.
 411 This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
 412
 413 As mentioned TBD, this leaves crops etc. to have a meaning defined for
 414 elwidth, because these ops are pure explicit CR based.
 415
 416 Examples: mfxm may take the extra bits and use them as extra mask bits.
 417
 418 # SUBVL Encoding
 419
 420 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
 421 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
 422 lines up in combination with all other "default is all zeros" behaviour.
 423
 424 | Value | Mnemonic  | Subvec  | Description            |
 425 |-------|-----------|---------|------------------------|
 426 | 00    | `SUBVL=1` | single  | Sub-vector length of 1 |
 427 | 01    | `SUBVL=2` | vec2    | Sub-vector length of 2 |
 428 | 10    | `SUBVL=3` | vec3    | Sub-vector length of 3 |
 429 | 11    | `SUBVL=4` | vec4    | Sub-vector length of 4 |
 430
 431 The SUBVL encoding value may be thought of as an inclusive range of a
 432 sub-vector.  SUBVL=2 represents a vec2, its encoding is 0b01, therefore
 433 this may be considered to be elements 0b00 to 0b01 inclusive.
 434
 435 # MASK/MASK_SRC & MASK_KIND Encoding
 436
 437 One bit (`MASKMODE`) indicates the mode: CR or Int predication.   The two
 438 types may not be mixed.
 439
 440 Special note: to get default behaviour (SV disabled) this field must
 441 be set to zero in combination with Integer Predication also being set
 442 to 0b000. this has the effect of enabling "all 1s" in the predicate
 443 mask, which is equivalent to "not having any predication at all"
 444 and consequently, in combination with all other default zeros, fully
 445 disables SV.
 446
 447 | Value | Description                                          |
 448 |-------|------------------------------------------------------|
 449 | 0     | MASK/MASK_SRC are encoded using Integer Predication  |
 450 | 1     | MASK/MASK_SRC are encoded using CR-based Predication |
 451
 452 Integer Twin predication has a second set of 3 bits that uses the same
 453 encoding thus allowing either the same register (r3 or r10) to be used
 454 for both src and dest, or different regs (one for src, one for dest).
 455
 456 Likewise CR based twin predication has a second set of 3 bits, allowing
 457 a different test to be applied.
 458
 459 ## Integer Predication (MASK_KIND=0)
 460
 461 When the predicate mode bit is zero the 3 bits are interpreted as below.
 462 Twin predication has an identical 3 bit field similarly encoded.
 463
 464 | Value | Mnemonic | Element `i` enabled if:      |
 465 |-------|----------|------------------------------|
 466 | 000   | ALWAYS   | predicate effectively all 1s |
 467 | 001   | 1 << R3  | `i == R3`                    |
 468 | 010   | R3       | `R3 & (1 << i)` is non-zero  |
 469 | 011   | ~R3      | `R3 & (1 << i)` is zero      |
 470 | 100   | R10      | `R10 & (1 << i)` is non-zero |
 471 | 101   | ~R10     | `R10 & (1 << i)` is zero     |
 472 | 110   | R30      | `R30 & (1 << i)` is non-zero |
 473 | 111   | ~R30     | `R30 & (1 << i)` is zero     |
 474
 475 ## CR-based Predication (MASK_KIND=1)
 476
 477 When the predicate mode bit is one the 3 bits are interpreted as below.
 478 Twin predication has an identical 3 bit field similarly encoded
 479
 480 | Value | Mnemonic | Element `i` is enabled if     |
 481 |-------|----------|--------------------------|
 482 | 000   | lt       | `CR[offs+i].LT` is set   |
 483 | 001   | nl/ge    | `CR[offs+i].LT` is clear |
 484 | 010   | gt       | `CR[offs+i].GT` is set   |
 485 | 011   | ng/le    | `CR[offs+i].GT` is clear |
 486 | 100   | eq       | `CR[offs+i].EQ` is set   |
 487 | 101   | ne       | `CR[offs+i].EQ` is clear |
 488 | 110   | so/un    | `CR[offs+i].FU` is set   |
 489 | 111   | ns/nu    | `CR[offs+i].FU` is clear |
 490
 491 CR based predication.  TODO: select alternate CR for twin predication? see
 492 [[discussion]]  Overlap of the two CR based predicates must be taken
 493 into account, so the starting point for one of them must be suitably
 494 high, or accept that for twin predication VL must not exceed the range
 495 where overlap will occur, *or* that they use the same starting point
 496 but select different *bits* of the same CRs
 497
 498 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below).  Rc=1 operations start from CR8 (TBD).
 499