1 # SVP64 Zero-Overhead Loop Prefix Subsystem
4 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[Power|openpower]] v3.0B [[ISA|openpower/isa/]].
9 Credits and acknowledgements:
17 * NLnet Foundation, for funding
18 * OpenPOWER Foundation
23 * IBM for the Power ISA itself
28 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
29 * [[svp64/discussion]]
31 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
34 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
35 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
36 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045> External RFC ls010
37 * [[sv/branches]] chapter
47 Simple-V is a type of Vectorisation best described as a "Prefix Loop
48 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and
49 to the 8086 `REP`[^bib_rep] Prefix instruction. More advanced features are similar
50 to the Z80 `CPIR`[^bib_cpir] instruction. If naively viewed one-dimensionally as an
51 actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
52 Vector instructions on the SFFS Subset and closer to 10 million 64-bit
53 True-Scalable Vector instructions if introduced on VSX. SVP64, the
54 instruction format used by Simple-V, is therefore best viewed as an
55 orthogonal RISC-paradigm "Prefixing" subsystem instead.
57 [^bib_ldir]: [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
58 [^bib_cpir]: [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)
59 [^bib_rep]: [8086 REP](https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz)
61 Except where explicitly stated all bit numbers remain as in the rest of
62 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
63 the left and counting up as you move rightwards to the LSB end). All bit
64 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
65 **All register numbering and element numbering however is LSB0 ordering**
66 which is a different convention from that used elsewhere in the Power ISA.
68 The SVP64 prefix always comes before the suffix in PC order and must be
69 considered an independent "Defined word" that augments the behaviour of
70 the following instruction, but does **not** change the actual Decoding
71 of that following instruction. **All SVP64-prefixed 32-bit instructions
72 (Defined Words) retain their non-prefixed encoding and definition**.
74 Two apparent exceptions to the above hard rule exist: SV
75 Branch-Conditional operations and LD/ST-update "Post-Increment"
76 Mode. Post-Increment was considered sufficiently high priority
77 (significantly reducing hot-loop instruction count) that one bit in
78 the Prefix is reserved for it (*Note the intention to release that bit
79 and move Post-Increment instructions to EXT2xx, as part of [[sv/rfc/ls011]]*).
80 Vectorised Branch-Conditional operations "embed" the original Scalar
81 Branch-Conditional behaviour into a much more advanced variant that is
82 highly suited to High-Performance Computation (HPC), Supercomputing,
83 and parallel GPU Workloads.
85 *Architectural Resource Allocation note: at present it is possible to perform
86 partial parallel decode of the SVP64 24-bit Encoding at the same time
87 as decoding of the Suffix. Multi-Issue Implementations may even
88 Decode multiple 32-bit words in parallel and follow up with a second
89 cycle of joining Prefix and Suffix "after-the-fact".
90 Mixing and overlaying 64-bit Opcode Encodings into the
91 {SVP64 24-bit Prefix}{Defined word-instruction} space creates
92 a hard dependency that catastrophically damages Multi-Issue Decoding.
93 Therefore it has to be prohibited to accept RFCs
94 which fundamentally violate this hard requirement. Under no circumstances
95 must the Suffix space have an alternate instruction encoding allocated
96 that is entirely different from the non-prefixed Defined
99 Subset implementations in hardware are permitted, as long as certain
100 rules are followed, allowing for full soft-emulation including future
101 revisions. Compliancy Subsets exist to ensure minimum levels of binary
102 interoperability expectations within certain environments. Details in
103 the [[svp64/appendix]].
105 ## SVP64 encoding features
107 A number of features need to be compacted into a very small space of
110 * Independent per-register Scalar/Vector tagging and range extension on
112 * Element width overrides on both source and destination
113 * Predication on both source and destination
114 * Two different sources of predication: INT and CR Fields
115 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
118 Different classes of operations require different formats. The earlier
119 sections cover the common formats and the five separate modes have their own
121 CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
122 Immediate, Load/Store Indexed, and Branch-Conditional.
124 ## Definition of Reserved in this spec.
126 For the new fields added in SVP64, instructions that have any of their
127 fields set to a reserved value must cause an illegal instruction trap,
128 to allow emulation of future instruction sets, or for subsets of SVP64 to
129 be implemented in hardware and the rest emulated. This includes SVP64
130 SPRs: reading or writing values which are not supported in hardware
131 must also raise illegal instruction traps in order to allow emulation.
132 Unless otherwise stated, reserved values are always all zeros.
134 This is unlike OpenPower ISA v3.1, which in many instances does not
135 require a trap if reserved fields are nonzero, instead relying on software
136 to avoid use of such fields. Where the standard Power
137 ISA definition is intended the red keyword `RESERVED` is used.
139 ## Definition of "PO9-Prefixed"
141 Used in the context of "A PO9-Prefixed Word" this is a new area similar to EXT100-163
142 that is shared between SVP64-Single, SVP64, 32 Vectorizable new Opcode areas
143 EXT200-231, one RESERVED 57-bit future Opcode space, and three new Unvectorizable
144 RESERVED 32-bit future Opcode spaces. See [[sv/po9_encoding]].
146 ## Definition of "SVP64-Prefix"
148 A 24-bit RISC-Paradigm Encoding area for Loop-Augmentation of the following
149 "Defined word-instruvtion".
150 Used in the context of "An SVP64-Prefixed Defined Word-instruction", as separate and
151 distinct from the 32-bit PO9-Prefix that holds a 24-bit SVP64 Prefix.
153 ## Definition of "Vectorizable" and "Unvectorizable"
155 "Vectorizable" Defined Word-instructions are Scalar instructions that
156 benefit from SVP64 Loop-Prefixing.
157 Conversely, any operation that inherently makes no sense if repeated in a
158 Vector Loop is termed
159 "Unvectorizable" or "Unvectorized". Examples include `sc` or `sync`
160 which have no registers. `mtmsr` is also classed as Unvectorizable
161 because there is only one `MSR`.
163 UnVectorized instructions are required to be detected as such if
164 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
167 *Architectural Note: Given that a "pre-classification" Decode Phase is
168 required (identifying whether the Suffix - Defined Word - is
169 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
170 adding "Unvectorised" to this phase is not unreasonable.*
172 Vectorizable Defined Word-instructions are **required** to be Vectorized,
173 or they may not be permitted to be added at all to the Power ISA as Defined
176 *Engineering note: implementations may not choose to add Defined Word-instructions
177 without also adding hardware support for SVP64-Prefixing of the same.*
179 *ISA Working Group note: Vectorized PackedSIMD instructions if ever proposed
180 should be considered Unvectorizable and except in extreme mitigating circumstances
183 ## Definition of Strict Program Order
185 Strict Program Order is defined as giving the appearance, as far
186 as programs are concerned, that instructions were executed
187 strictly in the sequence that they occurred. A "Precise"
189 Micro-architecture goes to considerable lengths to ensure that
192 Many Vector ISAs allow interrupts to occur in the middle of
193 processing of large Vector operations, only under the condition
194 that partial results are cleanly discarded, and continuation on return
195 from the Trap Handler will restart the entire operation.
196 The reason is that saving of full Architectural State is
197 not practical. An example would be a Floating-Point Horizontal Sum instruction
198 (very common in Vector ISAs) or a Dot Product instruction
199 that specifies a higher degree of accuracy for the *internal*
200 accumulator than the registers.
202 Simple-V operates on an entirely different paradigm from traditional
203 Vector ISAs: as a Sub-Program Counter where "Elements" are synonymous
204 with Scalar instructions. With this in mind it is critical for
205 implementations to observe Strict Element-Level Program Order
207 (often simply referred to as just "Strict Program Order"
210 *Any* element is Interruptible and Simple-V has
211 been carefully designed to guarantee that Architectural State may
212 be fully preserved and restored regardless of that same State, but
213 it is not necessarily guaranteed that the amount of time needed to recover
214 will be low latency (particularly if REMAP
217 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
218 but the full SVP64 Architectural State may be saved and
219 restored through manual copying of `SVSTATE` (and the four
220 REMAP SPRs if in use at the time)
221 Whilst this initially sounds unsafe in reality
222 all that Trap Handlers (and function call stack save/restore)
224 use of SVP64 Prefixed instructions to perform the necessary
225 save/restore of Simple-V Architectural State.
226 This capability also allows nested function calls to be made from
227 inside Vertical-First Vector loops, which is very rare for Vector ISAs.
229 Strict Program Order is also preserved by the Parallel Reduction
230 REMAP Schedule, but only at the cost of requiring the destination
231 Vector to be used (Deterministically) to store partial progress of the
234 The only major caveat for REMAP is that
235 after an explicit change to
236 Architectural State caused by writing to the
237 Simple-V SPRs, some implementations may find
238 it easier to take longer to calculate where in a given Schedule
239 the re-mapping Indices were. Obvious examples include Interrupts occuring
240 in the middle of a non-RADIX2 Matrix Multiply Schedule (5x3 by 3x3
242 will force implementations to perform divide and modulo
245 An additional caveat involves Condition Register Fields
246 when also used as Predicate Masks. An operation that
247 overwrites the same CR Fields that are simultaneously
248 being used as a Predicate Mask should exercise extreme care
249 if the overwritten CR field element was needed by a
250 subsequent Element for its Predicate Mask bit.
252 Some implementations may deploy Cray's technique of
253 "Vector Chaining" (including in this case reading the CR field
254 containing the Predicate bit until the very last moment),
255 and consequently avoiding the risk of
256 overwrite is the responsibility of the Programmer.
257 `hphint` may be used here to good effect.
258 Extra Special care is particularly needed here when using REMAP
259 and also Vertical-First Mode.
261 The simplest option is to use Integer Predicate Masks but the
262 caveats are stricter:
264 * In Vertical-First loops Programmers **must not** write to any
265 Integers (r3, r0, r31) used as Predicate Masks. Doing so
266 is `UNDEFINED` behaviour.
267 * An **entire** Vector is held up on Horizontal-First Mode if the
268 Integer Predicate is still in in-flight Reservation Stations
269 or pipelines. Speculative Vector Chained Execution mitigates delays
270 but can be heavy on Reservation Station resources.
272 ## Register files, elements, and Element-width Overrides
274 The relationship between register files, elements, and element-width
275 overrides is expressed as follows:
277 * register files are considered to be *byte-level* contiguous SRAMs,
278 accessed exclusively in Little-Endian Byte-Order at all times
279 * elements are sequential contiguous unbounded arrays starting at the "address"
280 of any given 64-bit GPR or FPR, numbered from 0 as the first,
281 "spilling" into numerically-sequentially-increasing GPRs
282 * element-width overrides set the width of the *elements* in the
283 sequentially-numbered contiguous array.
285 The relationship is best defined in Canonical form, below, in ANSI c as a
286 union data structure. A key difference is that VSR elements are bounded
287 fixed at 128-bit, where SVP64 elements are conceptually unbounded and
288 only limited by the Maximum Vector Length.
290 *Future specification note: SVP64 may be defined on top of VSRs in future.
291 At which point VSX also gains conceptually unbounded VSR register elements*
293 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR
294 Register files are expanded from 32 to 128 entries, and the number of
295 CR Fields expanded from CR0-CR7 to CR0-CR127. (Note: A future version
296 of SVP64 is anticipated to extend the VSR register file).
298 Memory access remains exactly the same: the effects of `MSR.LE` remain
299 exactly the same, affecting as they already do and remain **only**
300 on the Load and Store memory-register operation byte-order, and having
301 nothing to do with the ordering of the contents of register files or
302 register-register arithmetic or logical operations.
304 The only major impact on Arithmetic and Logical operations is that all
305 Scalar operations are defined, where practical and workable, to have
306 three new widths: elwidth=32, elwidth=16, elwidth=8.
308 *Architectural note: a future revision of SVP64 for VSX may have entirely
309 different definitions of possible elwidths.*
312 elwidth=64 is the pre-existing (Scalar) behaviour which remains 100%
313 unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit
314 variant of `addi`, but the sole exclusive difference is the width.
315 *In no way* is the actual `addi` instruction fundamentally altered
316 to become an entirely different operation (such as a subtract or multiply).
317 FP Operations elwidth overrides are also defined, as explained in
318 the [[svp64/appendix]].
320 To be absolutely clear:
323 There are no conceptual arithmetic ordering or other changes over the
324 Scalar Power ISA definitions to registers or register files or to
325 arithmetic or Logical Operations, beyond element-width subdivision
329 numbering is naturally **LSB0-sequentially-incrementing from zero, not
330 MSB0-incrementing** including when element-width overrides are used,
331 at which point the elements progress through each register
332 sequentially from the LSB end
333 (confusingly numbered the highest in MSB0 ordering) and progress
334 incrementally to the MSB end (confusingly numbered the lowest in
337 When exclusively using MSB0-numbering, SVP64 becomes unnecessarily complex
338 to both express and subsequently understand: the required conditional
339 subtractions from 63, 31, 15 and 7 needed to express the fact that
340 elements are LSB0-sequential unfortunately become a hostile minefield,
341 obscuring both intent and meaning. Therefore for the purposes of this
342 section the more natural **LSB0 numbering is assumed** and it is left
343 to the reader to translate to MSB0 numbering.
345 The Canonical specification for how element-sequential numbering and
346 element-width overrides is defined is expressed in the following c
347 structure, assuming a Little-Endian system, and naturally using LSB0
348 numbering everywhere because the ANSI c specification is inherently LSB0.
349 Note the deliberate similarity to how VSX register elements are defined,
350 from Figure 97, Book I, Section 6.3, Page 258:
355 uint8_t actual_bytes[8];
356 // all of these are very deliberately unbounded arrays
357 // that intentionally "wrap" into subsequent actual_bytes...
358 uint8_t bytes[]; // elwidth 8
359 uint16_t hwords[]; // elwidth 16
360 uint32_t words[]; // elwidth 32
361 uint64_t dwords[]; // elwidth 64
365 // ... here, as packed statically-defined GPRs.
366 elreg_t int_regfile[128];
368 // use element 0 as the destination
369 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
371 case 64: el->dwords[0] = int_regfile[gpr].dwords[element];
372 case 32: el->words[0] = int_regfile[gpr].words[element];
373 case 16: el->hwords[0] = int_regfile[gpr].hwords[element];
374 case 8 : el->bytes[0] = int_regfile[gpr].bytes[element];
378 // use element 0 as the source
379 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
381 case 64: int_regfile[gpr].dwords[element] = el->dwords[0];
382 case 32: int_regfile[gpr].words[element] = el->words[0];
383 case 16: int_regfile[gpr].hwords[element] = el->hwords[0];
384 case 8 : int_regfile[gpr].bytes[element] = el->bytes[0];
389 Example Vector-looped add operation implementation when elwidths are 64-bit:
392 # vector-add RT, RA,RB using the "uint64_t" union member, "dwords"
394 int_regfile[RT].dword[i] = int_regfile[RA].dword[i] + int_regfile[RB].dword[i]
397 However if elwidth overrides are set to 16 for both source and destination:
400 # vector-add RT, RA, RB using the "uint64_t" union member "hwords"
402 int_regfile[RT].hwords[i] = int_regfile[RA].hwords[i] + int_regfile[RB].hwords[i]
405 The most fundamental aspect here to understand is that the wrapping
406 into subsequent Scalar GPRs that occurs on larger-numbered elements
407 including and especially on smaller element widths is **deliberate
408 and intentional**. From this Canonical definition it should be clear
409 that sequential elements begin at the LSB end of any given underlying
410 Scalar GPR, progress to the MSB end, and then to the LSB end of the
411 *next numerically-larger Scalar GPR*. In the example above if VL=5
412 and RT=1 then the contents of GPR(1) and GPR(2) will be as follows.
413 For clarity in the table below:
415 * Both MSB0-ordered bitnumbering *and* LSB-ordered bitnumbering are shown
416 * The GPR-numbering is considered LSB0-ordered
417 * The Element-numbering (result0-result4) is LSB0-ordered
418 * Each of the results (result0-result4) are 16-bit
419 * "same" indicates "no change as a result of the Vectorised add"
422 | MSB0: | 0:15 | 16:31 | 32:47 | 48:63 |
423 | LSB0: | 63:48 | 47:32 | 31:16 | 15:0 |
424 |--------|---------|---------|---------|---------|
425 | GPR(0) | same | same | same | same |
426 | GPR(1) | result3 | result2 | result1 | result0 |
427 | GPR(2) | same | same | same | result4 |
428 | GPR(3) | same | same | same | same |
429 | ... | ... | ... | ... | ... |
430 | ... | ... | ... | ... | ... |
433 Note that the upper 48 bits of GPR(2) would **not** be modified due to
434 the example having VL=5. Thus on "wrapping" - sequential progression
435 from GPR(1) into GPR(2) - the 5th result modifies **only** the bottom
438 If the 16-bit operation were to be followed up with a 32-bit Vectorised
439 Operation, the exact same contents would be viewed as follows:
442 | MSB0: | 0:31 | 32:63 |
443 | LSB0: | 63:32 | 31:0 |
444 |--------|----------------------|----------------------|
445 | GPR(0) | same | same |
446 | GPR(1) | (result3 || result2) | (result1 || result0) |
447 | GPR(2) | same | (same || result4) |
448 | GPR(3) | same | same |
453 In other words, this perspective really is no different from the situation
454 where the actual Register File is treated as an Industry-standard
455 byte-level-addressable Little-Endian-addressed SRAM. Note that
456 this perspective does **not** involve `MSR.LE` in any way shape or
457 form because `MSR.LE` is directly in control of the Memory-to-Register
458 byte-ordering. This section is exclusively about how to correctly perceive
459 Simple-V-Augmented **Register** Files.
461 *Engineering note: to avoid a Read-Modify-Write at the register
462 file it is strongly recommended to implement byte-level write-enable lines
463 exactly as has been implemented in DRAM ICs for many decades. Additionally
464 the predicate mask bit is advised to be associated with the element
465 operation and alongside the result ultimately passed to the register file.
466 When element-width is set to 64-bit the relevant predicate mask bit
467 may be repeated eight times and pull all eight write-port byte-level
468 lines HIGH. Clearly when element-width is set to 8-bit the relevant
469 predicate mask bit corresponds directly with one single byte-level
470 write-enable line. It is up to the Hardware Architect to then amortise
471 (merge) elements together into both PredicatedSIMD Pipelines as well
472 as simultaneous non-overlapping Register File writes, to achieve High
473 Performance designs. Overall it helps to think of the GPR and FPR
474 register files as being much more akin to a 64-bit-wide byte-level-addressable SRAM.*
476 **Comparative equivalent using VSR registers**
478 For a comparative data point the VSR Registers may be expressed in the
479 same fashion. The c code below is directly an expression of Figure 97 in
480 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating
481 for MSB0 numbering in both bits and elements, adapting in full to LSB0
482 numbering, and obeying LE ordering*.
484 **Crucial to understanding why the subtraction from 1,3,7,15 is present is
485 because the Power ISA numbers VSX Registers elements also in MSB0 order**.
486 SVP64 very specifically numbers elements in **LSB0** order with the first
487 element (numbered zero) being at the bitwise-numbered **LSB** end of the
488 register, where VSX does the reverse: places the numerically-*highest*
489 (last-numbered) element at the LSB end of the register.
494 // these do NOT match their Power ISA VSX numbering directly, they are all reversed
495 // bytes[15] is actually VSR.byte[0] for example. if this convention is not
496 // followed then everything ends up in the wrong place
497 uint8_t bytes[16]; // elwidth 8, QTY 16 FIXED total
498 uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total
499 uint32_t words[4]; // elwidth 32, QTY 8 FIXED total
500 uint64_t dwords[2]; // elwidth 64, QTY 2 FIXED total
501 uint8_t actual_bytes[16]; // totals 128-bit
504 elreg_t VSR_regfile[64];
506 static void check_num_elements(int elt, int width) {
508 case 64: assert elt < 2;
509 case 32: assert elt < 4;
510 case 16: assert elt < 8;
511 case 8 : assert elt < 16;
514 void get_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
515 check_num_elements(elt, width);
517 case 64: el->dwords[0] = VSR_regfile[gpr].dwords[1-elt];
518 case 32: el->words[0] = VSR_regfile[gpr].words[3-elt];
519 case 16: el->hwords[0] = VSR_regfile[gpr].hwords[7-elt];
520 case 8 : el->bytes[0] = VSR_regfile[gpr].bytes[15-elt];
523 void set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
524 check_num_elements(elt, width);
526 case 64: VSR_regfile[gpr].dwords[1-elt] = el->dwords[0];
527 case 32: VSR_regfile[gpr].words[3-elt] = el->words[0];
528 case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[0];
529 case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[0];
534 For VSR Registers one key difference is that the overlay of different
535 element widths is clearly a *bounded static quantity*, whereas for
536 Simple-V the elements are unrestrained and permitted to flow into
537 *successive underlying Scalar registers*. This difference is absolutely
538 critical to a full understanding of the entire Simple-V paradigm and
539 why element-ordering, bit-numbering *and register numbering* are all so
542 Implementations are not permitted to violate the Canonical
543 definition. Software will be critically relying on the wrapped (overflow)
544 behaviour inherently implied by the unbounded variable-length c arrays.
546 Illustrating the exact same loop with the exact same effect as achieved
547 by Simple-V we are first forced to create wrapper functions, to cater
548 for the fact that VSR register elements are static bounded:
551 int calc_VSR_reg_offs(int elt, int width) {
553 case 64: return floor(elt / 2);
554 case 32: return floor(elt / 4);
555 case 16: return floor(elt / 8);
556 case 8 : return floor(elt / 16);
559 int calc_VSR_elt_offs(int elt, int width) {
561 case 64: return (elt % 2);
562 case 32: return (elt % 4);
563 case 16: return (elt % 8);
564 case 8 : return (elt % 16);
567 void _set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
568 int new_elt = calc_VSR_elt_offs(elt, width);
569 int new_reg = calc_VSR_reg_offs(elt, width);
570 set_VSR_element(el, gpr+new_reg, new_elt, width);
574 And finally use these functions:
577 # VSX-add RT, RA, RB using the "uint64_t" union member "hwords"
579 el_reg_t result, ra, rb;
580 _get_VSR_element(&ra, RA, i, 16);
581 _get_VSR_element(&rb, RB, i, 16);
582 result.hwords[0] = ra.hwords[0] + rb.hwords[0]; // use array 0 elements
583 _set_VSR_element(&result, RT, i, 16);
587 ## Scalar Identity Behaviour
589 SVP64 is designed so that when the prefix is all zeros, and VL=1, no
590 effect or influence occurs (no augmentation) such that all standard Power
591 ISA v3.0/v3.1 instructions covered by the prefix are "unaltered". This
592 is termed `scalar identity behaviour` (based on the mathematical
593 definition for "identity", as in, "identity matrix" or better "identity
596 Note that this is completely different from when VL=0. VL=0 turns all
597 operations under its influence into `nops` (regardless of the prefix)
598 whereas when VL=1 and the SV prefix is all zeros, the operation simply
599 acts as if SV had not been applied at all to the instruction (an
600 "identity transformation").
602 The fact that `VL` is dynamic and can be set to any value at runtime
603 based on program conditions and behaviour means very specifically that
604 `scalar identity behaviour` is **not** a redundant encoding. If the only
605 means by which VL could be set was by way of static-compiled immediates
606 then this assertion would be false. VL should not be confused with
607 MAXVL when understanding this key aspect of SimpleV.
609 ## Register Naming and size
611 As indicated above SV Registers are simply the GPR, FPR and CR register
612 files extended linearly to larger sizes; SV Vectorisation iterates
613 sequentially through these registers (LSB0 sequential ordering from 0
616 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
617 r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV)
618 as r0 to r127. Likewise FP registers are
619 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
620 CR0 thru CR127. In the Lower SV Compliancy Levels the quantity of registers
621 remains the same in order to reduce implementation cost for Embedded systems.
623 The names of the registers therefore reflects a simple linear extension
624 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
625 would be reflected by a linear increase in the size of the underlying
626 SRAM used for the regfiles.
628 Note: when an EXTRA field (defined below) is zero, SV is deliberately
629 designed so that the register fields are identical to as if SV was not in
630 effect i.e. under these circumstances (EXTRA=0) the register field names
631 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
632 This is part of `scalar identity behaviour` described above.
634 **Condition Register(s)**
636 The Scalar Power ISA Condition Register is a 64 bit register where
637 the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used.
638 This convention is *preserved* in SVP64 and an additional 15 Condition
639 Registers provided in order to store the new CR Fields, CR8-CR15,
640 CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition
641 Register are *also* not used: only the bottom 32 bits (numbered 32:63
644 *Programmer's note: using `sv.mfcr` without element-width overrides
645 to take into account the fact that the top 32 MSBs are zero and thus
646 effectively doubling the number of GPR registers required to hold all 128
647 CR Fields would seem the only option because a source elwidth override
648 to 32-bit would take only the bottom 16 LSBs of the Condition Register
649 and set the top 16 LSBs to zeros. However in this case it
650 is possible to use destination element-width overrides (for `sv.mfcr`.
651 source overrides would be used on the GPR of `sv.mtocrf`), whereupon
652 truncation of the 64-bit Condition Register(s) occurs, throwing away
653 the zeros and storing the remaining (valid, desired) 32-bit values
654 sequentially into (LSB0-convention) lower-numbered and upper-numbered
655 halves of GPRs respectively. The programmer is expected to be aware
656 however that the full width of the entire 64-bit Condition Register
657 is considered to be "an element". This is **not** like any other
658 Condition-Register instructions because all other CR instructions,
659 on closer investigation, will be observed to all be CR-bit or CR-Field
660 related. Thus a `VL` of 16 must be used*
662 **Condition Register Fields as Predicate Masks**
664 Condition Register Fields perform an additional duty in Simple-V: they are
665 used for Predicate Masks. ARM's Scalar Instruction Set calls single-bit
666 predication "Conditional Execution", and utilises Condition Codes for
667 exactly this purpose to solve the problem caused by Branch Speculation.
668 In a Vector ISA context the concept of Predication is naturally extended
669 from single-bit to multi-bit, and the (well-known) benefits become all the
670 more critical given that parallel branches in Vector ISAs are impossible
671 (even a Vector ISA can only have Scalar branches).
673 However the Scalar Power ISA does not have Conditional Execution (for
674 which, if it had ever been considered, Condition Register bits would be
675 a perfect natural fit). Thus, when adding Predication using CR Fields
676 via Simple-V it becomes a somewhat disruptive addition to the Power ISA.
678 To ameliorate this situation, particularly for pre-existing Hardware
679 designs implementing up to Scalar Power ISA v3.1, some rules are set that
680 allow those pre-existing designs not to require heavy modification to
681 their existing Scalar pipelines. These rules effectively allow Hardware
682 Architects to add the additional CR Fields CR8 to CR127 as if they were
683 an **entirely separate register file**.
685 * any instruction involving more than 1 source 1 destination
686 where one of the operands is a Condition Register is prohibited from
687 using registers from both the CR0-7 group and the CR8-127 group at
689 * any instruction involving 1 source 1 destination where either the
690 source or the destination is a Condition Register is prohibited
691 from setting CR0-7 as a Vector.
692 * prohibitions are required to be enforced by raising Illegal Instruction
695 Examples of permitted instructions:
698 sv.crand *cr8.eq, *cr16.le, *cr40.so # all CR8-CR127
699 sv.mfcr cr5, *cr40 # only one source (CR40) copied to CR5
700 sv.mfcr *cr16, cr40 # Vector-Splat CR40 onto CR16,17,18...
701 sv.mfcr *cr16, cr3 # Vector-Splat CR3 onto CR16,17,18...
704 Examples of prohibited instructions:
707 sv.mfcr *cr0, cr40 # Vector-Splat onto CR0,1,2
708 sv.crand cr7, cr9, cr10 # crosses over between CR0-7 and CR8-127
713 With the way that EXTRA fields are defined and applied to register
714 fields, future versions of SV may involve 256 or greater registers
715 in some way as long as the reputation of Power ISA for full backwards
716 binary interoperability is preserved. Backwards binary compatibility
717 may be achieved with a PCR bit (Program Compatibility Register) or an
718 MSR bit analogous to SF. Further discussion is out of scope for this
721 Additionally, a future variant of SVP64 will be applied to the Scalar
722 (Quad-precision and 128-bit) VSX instructions. Element-width overrides are
723 an opportunity to expand a future version of the Power ISA to 256-bit,
724 512-bit and 1024-bit operations, as well as doubling or quadrupling the
725 number of VSX registers to 128 or 256. Again further discussion is out
726 of scope for this version of SVP64.
732 ## SVP64 Remapped Encoding (`RM[0:23]`)
734 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits
735 32-37 are the Primary Opcode of the Suffix "Defined Word". 38-63 are the
736 remainder of the Defined Word. Note that the new EXT232-263 SVP64 area
737 it is obviously mandatory that bit 32 is required to be set to 1.
739 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
740 |-----|---|---|----------|--------|----------|-----------------------|
741 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
742 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
744 It is important to note that unlike EXT1xx 64-bit prefixed instructions
745 there is insufficient space in `RM` to provide identification of
746 any SVP64 Fields without first partially decoding the 32-bit suffix.
747 Similar to the "Forms" (X-Form, D-Form) the `RM` format is individually
748 associated with every instruction. However this still does not adversely
749 affect Multi-Issue Decoding because the identification of the *length*
750 of anything in the 64-bit space has been kept brutally simple (EXT009),
751 and further decoding of any number of 64-bit Encodings in parallel at
752 that point is fully independent.
754 Extreme caution and care must be taken when extending SVP64
755 in future, to not create unnecessary relationships between prefix and
756 suffix that could complicate decoding, adding latency.
760 The following fields are common to all Remapped Encodings:
762 | Field Name | Field bits | Description |
763 |------------|------------|----------------------------------------|
764 | MASKMODE | `0` | Execution (predication) Mask Kind |
765 | MASK | `1:3` | Execution Mask |
766 | SUBVL | `8:9` | Sub-vector length |
768 The following fields are optional or encoded differently depending
769 on context after decoding of the Scalar suffix:
771 | Field Name | Field bits | Description |
772 |------------|------------|----------------------------------------|
773 | ELWIDTH | `4:5` | Element Width |
774 | ELWIDTH_SRC | `6:7` | Element Width for Source (or MASK_SRC in 2PM) |
775 | EXTRA | `10:18` | Register Extra encoding |
776 | MODE | `19:23` | changes Vector behaviour |
778 * MODE changes the behaviour of the SV operation (result saturation,
780 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
781 and Audio/Video DSP work
782 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
784 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
785 sources: scalar INT and Vector CR).
786 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
787 for the instruction, which is determined only by decoding the Scalar 32
790 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
791 such as `RM-1P-3S1D` which indicates for this example that the operation
792 is to be single-predicated and that there are 3 source operand EXTRA
793 tags and one destination operand tag.
795 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
796 or increased latency in some implementations due to lane-crossing.
800 Mode is an augmentation of SV behaviour. Different types of instructions
801 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
802 formats apply to different instruction types. Modes include Reduction,
803 Iteration, arithmetic saturation, and Fail-First. More specific details
804 in each section and in the [[svp64/appendix]]
806 * For condition register operations see [[sv/cr_ops]]
807 * For LD/ST Modes, see [[sv/ldst]].
808 * For Branch modes, see [[sv/branches]]
809 * For arithmetic and logical, see [[sv/normal]]
813 Default behaviour is set to 0b00 so that zeros follow the convention
814 of `scalar identity behaviour`. In this case it means that elwidth
815 overrides are not applicable. Thus if a 32 bit instruction operates
816 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
817 Likewise when a processor is switched from 64 bit to 32 bit mode,
818 `elwidth=0b00` states that, again, the behaviour is not to be modified.
820 Only when elwidth is nonzero is the element width overridden to the
821 explicitly required value.
823 ### Elwidth for Integers:
825 | Value | Mnemonic | Description |
826 |-------|----------------|------------------------------------|
827 | 00 | DEFAULT | default behaviour for operation |
828 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
829 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
830 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
832 This encoding is chosen such that the byte width may be computed as
835 ### Elwidth for FP Registers:
837 | Value | Mnemonic | Description |
838 |-------|----------------|------------------------------------|
839 | 00 | DEFAULT | default behaviour for FP operation |
840 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
841 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
842 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
845 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
846 is reserved for a future implementation of SV
848 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`)
849 shall perform its operation at **half** the ELWIDTH then padded back out
850 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation
851 that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
852 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
853 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
854 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16 or
855 ELWIDTH=bf16 is reserved and must raise an illegal instruction (IEEE754
856 FP8 or BF8 are not defined).
858 ### Elwidth for CRs (no meaning)
860 Element-width overrides for CR Fields has no meaning. The bits
861 are therefore used for other purposes, or when Rc=1, the Elwidth
862 applies to the result being tested (a GPR or FPR), but not to the
867 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
868 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
869 lines up in combination with all other "default is all zeros" behaviour.
871 | Value | Mnemonic | Subvec | Description |
872 |-------|-----------|---------|------------------------|
873 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
874 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
875 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
876 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
878 The SUBVL encoding value may be thought of as an inclusive range of a
879 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
880 this may be considered to be elements 0b00 to 0b01 inclusive.
882 Effectively, SUBVL is like a SIMD multiplier: instead of just 1
883 element operation issued, SUBVL element operations are issued (as an inner loop).
884 The key difference between VL looping and SUBVL looping
885 is that predication bits are applied per
886 **group**, rather than by individual element.
888 Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
890 ## MASK/MASK_SRC & MASKMODE Encoding
892 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
893 types may not be mixed.
895 Special note: to disable predication this field must be set to zero in
896 combination with Integer Predication also being set to 0b000. this has the
897 effect of enabling "all 1s" in the predicate mask, which is equivalent to
898 "not having any predication at all".
900 `MASKMODE` may be set to one of 2 values:
902 | Value | Description |
903 |-----------|------------------------------------------------------|
904 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
905 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
907 Integer Twin predication has a second set of 3 bits that uses the same
908 encoding thus allowing either the same register (r3, r10 or r31) to be
909 used for both src and dest, or different regs (one for src, one for dest).
911 Likewise CR based twin predication has a second set of 3 bits, allowing
912 a different test to be applied.
914 Note that it cannot necessarily be assumed that Predicate Masks
915 (whether INT or CR) are read in full *before* the operations proceed. In practice (for CR Fields)
916 this creates an unnecessary block on parallelism, prohibiting
917 "Vector Chaining". Therefore, it is up
918 to the programmer to ensure that the CR field Elements used as Predicate Masks
919 are not overwritten by any parallel Vector Loop. Doing so results
920 in **UNDEFINED** behaviour, according to the definition outlined in the
921 Power ISA v3.0B Specification.
923 Hardware Implementations are therefore free and clear to delay reading
924 of individual CR fields until the actual predicated element operation
925 needs to take place, safe in the knowledge that no programmer will have
926 issued a Vector Instruction where previous elements could have overwritten
927 (destroyed) not-yet-executed CR-Predicated element operations.
928 This particularly is an issue when using REMAP, as the order in
929 which CR-Field-based Predicate Mask bits could be read on a per-element
930 execution basis could well conflict with the order in which prior
931 elements wrote to the very same CR Field.
933 Additionally Programmers should avoid using r3 r10 or r30
934 as destination registers when these are also used as a Predicate
935 Mask. Doing so is again UNDEFINED behaviour.
937 Usually in 2P `MASK_SRC` is exclusively in the EXTRA area. However for
938 LD/ST-Indexed a different Encoding is required, designated `2PM`.
940 ### Integer Predication (MASKMODE=0)
942 When the predicate mode bit is zero the 3 bits are interpreted as below.
943 Twin predication has an identical 3 bit field similarly encoded.
945 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
948 | Value | Mnemonic | Element `i` enabled if: |
949 |-------|----------|------------------------------|
950 | 000 | ALWAYS | predicate effectively all 1s |
951 | 001 | 1 << R3 | `i == R3` |
952 | 010 | R3 | `R3 & (1 << i)` is non-zero |
953 | 011 | ~R3 | `R3 & (1 << i)` is zero |
954 | 100 | R10 | `R10 & (1 << i)` is non-zero |
955 | 101 | ~R10 | `R10 & (1 << i)` is zero |
956 | 110 | R30 | `R30 & (1 << i)` is non-zero |
957 | 111 | ~R30 | `R30 & (1 << i)` is zero |
959 r10 and r30 are at the high end of temporary and unused registers,
960 so as not to interfere with register allocation from ABIs.
962 ### CR-based Predication (MASKMODE=1)
964 When the predicate mode bit is one the 3 bits are interpreted as below.
965 Twin predication has an identical 3 bit field similarly encoded.
967 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
970 | Value | Mnemonic | Element `i` is enabled if |
971 |-------|----------|--------------------------|
972 | 000 | lt | `CR[offs+i].LT` is set |
973 | 001 | nl/ge | `CR[offs+i].LT` is clear |
974 | 010 | gt | `CR[offs+i].GT` is set |
975 | 011 | ng/le | `CR[offs+i].GT` is clear |
976 | 100 | eq | `CR[offs+i].EQ` is set |
977 | 101 | ne | `CR[offs+i].EQ` is clear |
978 | 110 | so/un | `CR[offs+i].FU` is set |
979 | 111 | ns/nu | `CR[offs+i].FU` is clear |
981 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised
982 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
984 The CR Predicates chosen must start on a boundary that Vectorised CR
985 operations can access cleanly, in full. With EXTRA2 restricting starting
986 points to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and
987 CR Predicate Masks have to be adapted to fit on these boundaries as well.
989 ## Extra Remapped Encoding <a name="extra_remap"> </a>
991 Shows all instruction-specific fields in the Remapped Encoding
992 `RM[10:18]` for all instruction variants. Note that due to the very
993 tight space, the encoding mode is *not* included in the prefix itself.
994 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
995 on a per-instruction basis, and, like "Forms" are given a designation
996 (below) of the form `RM-nP-nSnD`. The full list of which instructions
997 use which remaps is here [[opcode_regs_deduped]].
999 **Please note the following**:
1002 Machine-readable CSV files have been autogenerated which will make the
1003 task of creating SV-aware ISA decoders, documentation, assembler tools
1004 compiler tools Simulators documentation all aspects of SVP64 easier
1005 and less prone to mistakes. Please avoid manual re-creation of
1006 information from the written specification wording in this chapter,
1007 and use the CSV files or use the Canonical tool which creates the CSV
1008 files, named sv_analysis.py. The information contained within
1009 sv_analysis.py is considered to be part of this Specification, even
1010 encoded as it is in python3.
1014 The mappings are part of the SVP64 Specification in exactly the same
1015 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
1016 will need a corresponding SVP64 Mapping, which can be derived by-rote
1017 from examining the Register "Profile" of the instruction.
1019 There are two categories: Single and Twin Predication. Due to space
1020 considerations further subdivision of Single Predication is based on
1021 whether the number of src operands is 2 or 3. With only 9 bits available
1022 some compromises have to be made.
1024 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
1025 instructions (fmadd, isel, madd).
1026 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
1027 instructions (src1 src2 dest)
1028 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
1029 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
1030 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
1031 * `RM-2PM-2S1D` Twin Predication (src=2, dest=1) for LD/ST Update (Indexed)
1033 The `2PM` designation uses bits 6 and 7 as well as the 9 EXTRA bits
1034 in order to extend two registers to
1035 EXTRA3, sacrificing destination elwidths in the process.
1036 `MASK_SRC` has a different encoding in `2PM`.
1040 | Field Name | Field bits | Description |
1041 |------------|------------|----------------------------------------|
1042 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1043 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1044 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1045 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1046 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
1048 These are for 3 operand in and either 1 or 2 out instructions.
1049 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
1050 such as `maddedu` have an implicit second destination, RS, the
1051 selection of which is determined by bit 18.
1055 | Field Name | Field bits | Description |
1056 |------------|------------|-------------------------------------------|
1057 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
1058 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
1059 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
1061 These are for 2 operand 1 dest instructions, such as `add RT, RA,
1062 RB`. However also included are unusual instructions with an implicit
1063 dest that is identical to its src reg, such as `rlwinmi`.
1065 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
1066 not have sufficient bit fields to allow an alternative destination.
1067 With SV however this becomes possible. Therefore, the fact that the
1068 dest is implicitly also a src should not mislead: due to the *prefix*
1069 they are different SV regs.
1071 * `rlwimi RA, RS, ...`
1072 * Rsrc1_EXTRA3 applies to RS as the first src
1073 * Rsrc2_EXTRA3 applies to RA as the second src
1074 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
1076 With the addition of the EXTRA bits, the three registers
1077 each may be *independently* made vector or scalar, and be independently
1078 augmented to 7 bits in length.
1082 | Field Name | Field bits | Description |
1083 |------------|------------|----------------------------|
1084 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1085 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1086 | MASK_SRC | `16:18` | Execution Mask for Source |
1088 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
1090 | Field Name | Field bits | Description |
1091 |------------|------------|----------------------------|
1092 | Rsrc1_EXTRA3 | `10:12` | extends Rsrc1 |
1093 | Rsrc2_EXTRA3 | `13:15` | extends Rsrc2 |
1094 | MASK_SRC | `16:18` | Execution Mask for Source |
1098 single-predicate, three registers (2 read, 1 write)
1100 | Field Name | Field bits | Description |
1101 |------------|------------|----------------------------|
1102 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1103 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1104 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
1106 ### RM-2P-2S1D/1S2D/3S
1108 The primary purpose for this encoding is for Twin Predication on LOAD
1109 and STORE operations. see [[sv/ldst]] for detailed analysis.
1113 | Field Name | Field bits | Description |
1114 |------------|------------|----------------------------|
1115 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1116 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1117 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1118 | MASK_SRC | `16:18` | Execution Mask for Source |
1122 For RM-2P-1S2D dest2 is in bits 14:15
1124 | Field Name | Field bits | Description |
1125 |------------|------------|----------------------------|
1126 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1127 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1128 | Rdest2_EXTRA2 | `14:15` | extends Rdest22 (R\*\_EXTRA2 Encoding) |
1129 | MASK_SRC | `16:18` | Execution Mask for Source |
1133 Also that for RM-2P-3S (to cover `stdx` etc.) the names are switched to 3 src:
1134 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
1136 | Field Name | Field bits | Description |
1137 |------------|------------|----------------------------|
1138 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1139 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1140 | Rsrc3_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1141 | MASK_SRC | `16:18` | Execution Mask for Source |
1143 Note also that LD with update indexed, which takes 2 src and
1144 creates 2 dest registers (e.g. `lhaux RT,RA,RB`), does not have room
1145 for 4 registers and also Twin Predication. Therefore these are treated as
1146 RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest.
1148 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
1149 or increased latency in some implementations due to lane-crossing.
1151 ### RM-2PM-2S1D/1S2D/3S
1153 The primary purpose for this encoding is for Twin Predication on LOAD
1154 and STORE operations providing EXTRA3 for RT, RA and RS.
1155 see [[sv/ldst]] for detailed analysis.
1159 RT or RS requires EXTRA3, RA requires EXTRA3, but for RB EXTRA2 will
1160 suffice. `MASK_SRC` may be read from the bits normally used for dest-elwidth.
1162 | Field Name | Field bits | Description |
1163 |------------|------------|----------------------------|
1164 | Rdest_EXTRA3 | `10:12` | extends Rdest (R\*\_EXTRA2 Encoding) |
1165 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1166 | Rsrc2_EXTRA2 | `16:17` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1167 | MASK_SRC | `6:7,18` | Execution Mask for Source |
1171 EXTRA is the means by which two things are achieved:
1173 1. Registers are marked as either Vector *or Scalar*
1174 2. Register field numbers (limited typically to 5 bit)
1175 are extended in range, both for Scalar and Vector.
1177 The register files are therefore extended:
1179 * INT (GPR) is extended from r0-31 to r0-127
1180 * FP (FPR) is extended from fp0-32 to fp0-fp127
1181 * CR Fields are extended from CR0-7 to CR0-127
1183 However due to pressure in `RM.EXTRA` not all these registers
1184 are accessible by all instructions, particularly those with
1185 a large number of operands (`madd`, `isel`).
1187 In the following tables register numbers are constructed from the
1188 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
1189 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
1190 designation for a given instruction. The prefixing is arranged so that
1191 interoperability between prefixing and nonprefixing of scalar registers
1192 is direct and convenient (when the EXTRA field is all zeros).
1194 A pseudocode algorithm explains the relationship, for INT/FP (see
1195 [[svp64/appendix]] for CRs)
1201 spec = EXTRA2 << 1 # same as EXTRA3, shifted
1202 if spec[0]: # vector
1203 return (RA << 2) | spec[1:2]
1205 return (spec[1:2] << 5) | RA
1208 Future versions may extend to 256 by shifting Vector numbering up.
1209 Scalar will not be altered.
1211 Note that in some cases the range of starting points for Vectors
1216 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
1219 Fields are as follows:
1222 * Mode: register is tagged as scalar or vector
1223 * Range/Inc: the range of registers accessible from this EXTRA
1224 encoding, and the "increment" (accessibility). "/4" means
1225 that this EXTRA encoding may only give access (starting point)
1227 * MSB..LSB: the bit field showing how the register opcode field
1228 combines with EXTRA to give (extend) the register number (GPR)
1230 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1232 | Value | Mode | Range/Inc | 6..0 |
1233 |-----------|-------|---------------|---------------------|
1234 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
1235 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
1236 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
1237 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
1238 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
1239 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
1240 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
1241 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
1245 If EXTRA2 is zero will map to "scalar identity behaviour" i.e Scalar
1246 Power ISA register naming:
1248 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1250 | Value | Mode | Range/inc | 6..0 |
1251 |----------|-------|---------------|-----------|
1252 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
1253 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
1254 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
1255 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
1257 **Note that unlike in EXTRA3, in EXTRA2**:
1259 * the GPR Vectors may only start from
1260 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
1261 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
1263 as there is insufficient bits to cover the full range.
1267 CR Field encoding is essentially the same but made more complex due to CRs
1268 being bit-based, because the application of SVP64 element-numbering applies
1269 to the CR *Field* numbering not the CR register *bit* numbering.
1270 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
1271 and Scalars may only go from `CR0, CR1, ... CR31`
1273 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1274 BA ranges are in MSB0.
1276 For a 5-bit operand (BA, BB, BT):
1278 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1279 |-------|------|---------------|-----------| --------|---------|
1280 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1281 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1282 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
1283 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
1284 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1285 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
1286 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1287 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
1289 For a 3-bit operand (e.g. BFA):
1291 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1292 |-------|------|---------------|-----------| --------|
1293 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1294 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1295 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
1296 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
1297 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1298 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
1299 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1300 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
1304 CR encoding is essentially the same but made more complex due to CRs
1305 being bit-based, because the application of SVP64 element-numbering applies
1306 to the CR *Field* numbering not the CR register *bit* numbering.
1307 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
1309 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1310 BA ranges are in MSB0.
1312 For a 5-bit operand (BA, BB, BC):
1314 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1315 |-------|--------|----------------|---------|---------|---------|
1316 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1317 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1318 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1319 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1321 For a 3-bit operand (e.g. BFA):
1323 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1324 |-------|------|---------------|-----------| --------|
1325 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1326 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1327 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1328 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1333 Now at its own page: [[svp64/appendix]]