3 # SVP64 for OpenPOWER ISA v3.0B
7 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1 implementations has not yet been granted through the issuance of a v3.1 EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
11 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
12 * [[svp64/discussion]]
14 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
25 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
27 The plan is to create an encoding for SVP64, then to create an encoding
28 for SVP48, then to reorganize them both to improve field overlap,
29 reducing the amount of decoder hardware necessary.
31 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
32 and counting up as you move to the LSB end). All bit ranges are inclusive
33 (so `4:6` means bits 4, 5, and 6).
35 64-bit instructions are split into two 32-bit words, the prefix and the
36 suffix. The prefix always comes before the suffix in PC order.
39 |--------|--------------|--------------|
40 | EXT01 | v3.1 Prefix | v3.1 Suffix |
42 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
44 ## SVP64 encoding features
46 A number of features need to be compacted into a very small space of only 24 bits:
48 * Independent per-register Scalar/Vector tagging and range extension on every register
49 * Element width overrides on both source and destination
50 * Predication on both source and destination
51 * Two different *types* of predication: INT and CR
52 * SV Modes including saturation (for A/V DSP), mapreduce, fail-first and
53 predicate-result mode.
55 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
57 # Definition of Reserved in this spec.
59 For the new fields added in SVP64, instructions that have any of their
60 fields set to a reserved value must cause an illegal instruction trap,
61 to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
63 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
67 SVP64 is designed so that when the prefix is all zeros, and
69 influence occurs (no augmentation) such that all standard OpenPOWER
70 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
72 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
73 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
75 The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
77 # Register Naming and size
79 SV Registers are simply the INT, FP and CR register files extended
80 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
82 Where the integer regfile in standard scalar
83 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
84 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
85 extended to 128 entries, CR0 thru CR127.
87 The names of the registers therefore reflects a simple linear extension
88 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
89 would be reflected by a linear increase in the size of the underlying
90 SRAM used for the regfiles.
92 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
93 so that the register fields are identical to as if SV was not in effect
94 i.e. under these circumstances (EXTRA=0) the register field names RA,
95 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
96 `scalar identity behaviour` described above.
100 With the way that EXTRA fields are defined and applied to register fields,
101 future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
102 requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
104 # Remapped Encoding (`RM[0:23]`)
106 To allow relatively easy remapping of which portions of the Prefix Opcode
107 Map are used for SVP64 without needing to rewrite a large portion of the
108 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
109 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
112 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
113 is defined in the Prefix Fields section.
115 ## Prefix Opcode Map (64-bit instruction encoding)
117 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
119 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
120 empty spaces are yet-to-be-allocated Illegal Instructions.
122 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
123 |------|--------|--------|--------|--------|--------|--------|--------|--------|
124 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
125 |001---| | | | | | | | |
126 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
127 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
128 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
129 |101---| | | | | | | | |
130 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
131 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
133 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
137 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
138 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
139 This is achieved by setting bits 7 and 9 to 1:
141 | Name | Bits | Value | Description |
142 |------------|---------|-------|--------------------------------|
143 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
144 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
145 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
146 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
147 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
148 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
150 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
153 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
154 |--------|-------|---|-------|---|----------|
155 | EXT01 | RM | 1 | RM | 1 | RM |
156 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
158 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
159 instruction. That instruction becomes "prefixed" with the SVP context: the
160 Remapped Encoding field (RM).
164 The following fields are common to all Remapped Encodings:
166 | Field Name | Field bits | Description |
167 |------------|------------|----------------------------------------|
168 | MASKMODE | `0` | Execution (predication) Mask Kind |
169 | MASK | `1:3` | Execution Mask |
170 | ELWIDTH | `4:5` | Element Width |
171 | ELWIDTH_SRC | `6:7` | Element Width for Source |
172 | SUBVL | `8:9` | Sub-vector length |
173 | MODE | `19:23` | changes Vector behaviour |
175 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
176 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
177 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
178 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
180 Bits 10 to 18 are further decoded depending on RM category for the instruction.
181 Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
183 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
187 Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
189 These are the modes for everything except [[sv/ldst]] and [[sv/branches]]:
191 * **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results.
192 * **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria.
193 *VL is altered as a result*.
194 * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps. allows signed and unsigned clamping for both INT
196 * **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[appendix]]
197 note that there are comprehensive caveats when using this mode.
198 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the
199 *destination* predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details.
201 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
203 The Mode table for operations except LD/ST and Branch Conditional
204 is laid out as follows:
206 | 0-1 | 2 | 3 4 | description |
207 | --- | --- |---------|-------------------------- |
208 | 00 | 0 | dz sz | normal mode |
209 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
210 | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 |
211 | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
212 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
213 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
214 | 10 | N | dz sz | sat mode: N=0/1 u/s |
215 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
216 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
220 * **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context.
221 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
222 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
223 than the normal 0..VL-1
224 * **CRM** affects the CR on reduce mode when Rc=1
225 * **SVM** sets "subvector" reduce mode
226 * **N** sets signed/unsigned saturation.
227 * **RC1** as if Rc=1, stores CRs *but not the result*
228 * **VLi** VL inclusive: in fail-first mode, the truncation of
229 VL *includes* the current element at the failure point rather
230 than excludes it from the count.
232 For LD/ST Modes, see [[sv/ldst]]. For Branch modes, see [[sv/branches]] Immediate and Indexed LD/ST
233 are both different, in order to support a large range of features
234 normally found in Vector ISAs.
238 Default behaviour is set to 0b00 so that zeros follow the convention of
239 `scalar identity behaviour`. In this case it means that elwidth overrides
240 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
241 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
242 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
243 states that, again, the behaviour is not to be modified.
245 Only when elwidth is nonzero is the element width overridden to the
246 explicitly required value.
248 ## Elwidth for Integers:
250 | Value | Mnemonic | Description |
251 |-------|----------------|------------------------------------|
252 | 00 | DEFAULT | default behaviour for operation |
253 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
254 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
255 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
257 This encoding is chosen such that the byte width may be computed as `(3-ew)<<8`
259 ## Elwidth for FP Registers:
261 | Value | Mnemonic | Description |
262 |-------|----------------|------------------------------------|
263 | 00 | DEFAULT | default behaviour for FP operation |
264 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
265 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
266 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
269 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
270 is reserved for a future implementation of SV
274 TODO, important, particularly for crops, mfcr and mtcr, what elwidth
275 even means. instead it may be possible to use the bits as extra indices
276 (add to EXTRA2/3) to access the full 128 CRs at the bit level. TBD, several ideas
278 The actual width of the CRs cannot be altered: they are 4 bit. Also,
279 for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
280 the INT/FP result to which the elwidth override applies, *not* the CR.
281 This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
283 As mentioned TBD, this leaves crops etc. to have a meaning defined for
284 elwidth, because these ops are pure explicit CR based.
286 Examples: mfxm may take the extra bits and use them as extra mask bits.
288 Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review.
292 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
293 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
294 lines up in combination with all other "default is all zeros" behaviour.
296 | Value | Mnemonic | Subvec | Description |
297 |-------|-----------|---------|------------------------|
298 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
299 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
300 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
301 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
303 The SUBVL encoding value may be thought of as an inclusive range of a
304 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
305 this may be considered to be elements 0b00 to 0b01 inclusive.
307 # MASK/MASK_SRC & MASKMODE Encoding
309 TODO: rename MASK_KIND to MASKMODE
311 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
312 types may not be mixed.
314 Special note: to disable predication this field must
315 be set to zero in combination with Integer Predication also being set
316 to 0b000. this has the effect of enabling "all 1s" in the predicate
317 mask, which is equivalent to "not having any predication at all"
318 and consequently, in combination with all other default zeros, fully
319 disables SV (`scalar identity behaviour`).
321 `MASKMODE` may be set to one of 2 values:
323 | Value | Description |
324 |-----------|------------------------------------------------------|
325 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
326 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
328 Integer Twin predication has a second set of 3 bits that uses the same
329 encoding thus allowing either the same register (r3 or r10) to be used
330 for both src and dest, or different regs (one for src, one for dest).
332 Likewise CR based twin predication has a second set of 3 bits, allowing
333 a different test to be applied.
335 Note that it is assumed that Predicate Masks (whether INT or CR)
336 are read *before* the operations proceed. In practice (for CR Fields)
337 this creates an unnecessary block on parallelism. Therefore,
338 it is up to the programmer to ensure that the CR fields used as
339 Predicate Masks are not being written to by any parallel Vector Loop.
340 Doing so results in **UNDEFINED** behaviour, according to the definition
341 outlined in the OpenPOWER v3.0B Specification.
343 Hardware Implementations are therefore free and clear to delay reading
344 of individual CR fields until the actual predicated element operation
345 needs to take place, safe in the knowledge that no programmer will
346 have issued a Vector Instruction where previous elements could have
347 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
349 ## Integer Predication (MASKMODE=0)
351 When the predicate mode bit is zero the 3 bits are interpreted as below.
352 Twin predication has an identical 3 bit field similarly encoded.
354 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
356 | Value | Mnemonic | Element `i` enabled if: |
357 |-------|----------|------------------------------|
358 | 000 | ALWAYS | predicate effectively all 1s |
359 | 001 | 1 << R3 | `i == R3` |
360 | 010 | R3 | `R3 & (1 << i)` is non-zero |
361 | 011 | ~R3 | `R3 & (1 << i)` is zero |
362 | 100 | R10 | `R10 & (1 << i)` is non-zero |
363 | 101 | ~R10 | `R10 & (1 << i)` is zero |
364 | 110 | R30 | `R30 & (1 << i)` is non-zero |
365 | 111 | ~R30 | `R30 & (1 << i)` is zero |
367 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
369 ## CR-based Predication (MASKMODE=1)
371 When the predicate mode bit is one the 3 bits are interpreted as below.
372 Twin predication has an identical 3 bit field similarly encoded.
374 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
376 | Value | Mnemonic | Element `i` is enabled if |
377 |-------|----------|--------------------------|
378 | 000 | lt | `CR[offs+i].LT` is set |
379 | 001 | nl/ge | `CR[offs+i].LT` is clear |
380 | 010 | gt | `CR[offs+i].GT` is set |
381 | 011 | ng/le | `CR[offs+i].GT` is clear |
382 | 100 | eq | `CR[offs+i].EQ` is set |
383 | 101 | ne | `CR[offs+i].EQ` is clear |
384 | 110 | so/un | `CR[offs+i].FU` is set |
385 | 111 | ns/nu | `CR[offs+i].FU` is clear |
387 CR based predication. TODO: select alternate CR for twin predication? see
388 [[discussion]] Overlap of the two CR based predicates must be taken
389 into account, so the starting point for one of them must be suitably
390 high, or accept that for twin predication VL must not exceed the range
391 where overlap will occur, *or* that they use the same starting point
392 but select different *bits* of the same CRs
394 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
396 Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs.
398 # Extra Remapped Encoding
400 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
402 There are two categories: Single and Twin Predication.
403 Due to space considerations further subdivision of Single Predication
404 is based on whether the number of src operands is 2 or 3.
406 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
407 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
408 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
409 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
410 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
414 | Field Name | Field bits | Description |
415 |------------|------------|----------------------------------------|
416 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
417 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
418 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
419 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
420 | reserved | `18` | reserved |
424 | Field Name | Field bits | Description |
425 |------------|------------|-------------------------------------------|
426 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
427 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
428 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
430 These are for 2 operand 1 dest instructions, such as `add RT, RA,
431 RB`. However also included are unusual instructions with an implicit dest
432 that is identical to its src reg, such as `rlwinmi`.
434 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
435 an alternative destination. With SV however this becomes possible.
436 Therefore, the fact that the dest is implicitly also a src should not
437 mislead: due to the *prefix* they are different SV regs.
439 * `rlwimi RA, RS, ...`
440 * Rsrc1_EXTRA3 applies to RS as the first src
441 * Rsrc2_EXTRA3 applies to RA as the secomd src
442 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
444 With the addition of the EXTRA bits, the three registers
445 each may be *independently* made vector or scalar, and be independently
446 augmented to 7 bits in length.
450 | Field Name | Field bits | Description |
451 |------------|------------|----------------------------|
452 | Rdest_EXTRA3 | `10:12` | extends Rdest |
453 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
454 | MASK_SRC | `16:18` | Execution Mask for Source |
456 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
458 ## RM-2P-2S1D/1S2D/3S
460 The primary purpose for this encoding is for Twin Predication on LOAD
461 and STORE operations. see [[sv/ldst]] for detailed anslysis.
465 | Field Name | Field bits | Description |
466 |------------|------------|----------------------------|
467 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
468 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
469 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
470 | MASK_SRC | `16:18` | Execution Mask for Source |
472 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
473 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
475 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
477 Note also that LD with update indexed, which takes 2 src and 2 dest
478 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
479 Twin Predication. therefore these are treated as RM-2P-2S1D and the
480 src spec for RA is also used for the same RA as a dest.
482 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
486 EXTRA is the means by which two things are achieved:
488 1. Registers are marked as either Vector *or Scalar*
489 2. Register field numbers (limited typically to 5 bit)
490 are extended in range, both for Scalar and Vector.
492 The register files are therefore extended:
494 * INT is extended from r0-31 to 128
495 * FP is extended from fp0-32 to 128
496 * CR is extended from CR0-7 to CR0-127
498 In the following tables register numbers are constructed from the
499 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
500 or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
501 interoperability between prefixing and nonprefixing of scalar registers
502 is direct and convenient (when the EXTRA field is all zeros).
504 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
509 spec = EXTRA2 << 1 # same as EXTRA3, shifted
511 return (RA << 2) | spec[1:2]
513 return (spec[1:2] << 5) | RA
515 Future versions may extend to 256 by shifting Vector numbering up.
516 Scalar will not be altered.
520 alternative which is understandable and, if EXTRA3 is zero, maps to
521 "no effect" (scalar OpenPOWER ISA field naming). also, these are the
522 encodings used in the original SV Prefix scheme. the reason why they
523 were chosen is so that scalar registers in v3.0B and prefixed scalar
524 registers have access to the same 32 registers.
526 Fields are as follows:
529 * Mode: register is tagged as scalar or vector
530 * Range/Inc: the range of registers accessible from this EXTRA
531 encoding, and the "increment" (accessibility). "/4" means
532 that this EXTRA encoding may only give access (starting point)
534 * MSB..LSB: the bit field showing how the register opcode field
535 combines with EXTRA to give (extend) the register number (GPR)
537 | Value | Mode | Range/Inc | 6..0 |
538 |-----------|-------|---------------|---------------------|
539 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
540 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
541 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
542 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
543 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
544 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
545 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
546 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
550 alternative which is understandable and, if EXTRA2 is zero will map to
551 "no effect" i.e Scalar OpenPOWER register naming:
553 | Value | Mode | Range/inc | 6..0 |
554 |-----------|-------|---------------|-----------|
555 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
556 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
557 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
558 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
562 CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
564 Encoding shown MSB down to LSB
566 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
567 |-------|------|---------------|-----------| --------|---------|
568 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
569 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
570 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
571 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
572 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
573 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
574 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
575 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
579 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
581 Encoding shown MSB down to LSB
583 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
584 |-------|--------|----------------|---------|---------|---------|
585 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
586 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
587 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
588 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
592 Now at its own page: [[svp64/appendix]]