3 # DRAFT SVP64 for OpenPOWER ISA v3.0B
5 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1 implementations has not yet been granted through the issuance of a v3.1 EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
9 Credits and acknowledgements:
17 * NLnet Foundation, for funding
18 * OpenPOWER Foundation
21 * IBM for the Power ISA itself
25 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
26 * [[svp64/discussion]]
28 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
29 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
30 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
31 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
39 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
41 The plan is to create an encoding for SVP64, then to create an encoding
42 for SVP48, then to reorganize them both to improve field overlap,
43 reducing the amount of decoder hardware necessary.
45 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
46 and counting up as you move to the LSB end). All bit ranges are inclusive
47 (so `4:6` means bits 4, 5, and 6).
49 64-bit instructions are split into two 32-bit words, the prefix and the
50 suffix. The prefix always comes before the suffix in PC order.
53 |--------|--------------|--------------|
54 | EXT01 | v3.1 Prefix | v3.1 Suffix |
56 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
58 ## SVP64 encoding features
60 A number of features need to be compacted into a very small space of only 24 bits:
62 * Independent per-register Scalar/Vector tagging and range extension on every register
63 * Element width overrides on both source and destination
64 * Predication on both source and destination
65 * Two different *types* of predication: INT and CR
66 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
67 predicate-result mode.
69 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
71 # Definition of Reserved in this spec.
73 For the new fields added in SVP64, instructions that have any of their
74 fields set to a reserved value must cause an illegal instruction trap,
75 to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
77 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition
78 is intended the red keyword `RESERVED` is used.
82 SVP64 is designed so that when the prefix is all zeros, and
84 influence occurs (no augmentation) such that all standard OpenPOWER
85 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
87 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
88 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
90 The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
92 # Register Naming and size
94 SV Registers are simply the INT, FP and CR register files extended
95 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
97 Where the integer regfile in standard scalar
98 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
99 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
100 extended to 128 entries, CR0 thru CR127.
102 The names of the registers therefore reflects a simple linear extension
103 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
104 would be reflected by a linear increase in the size of the underlying
105 SRAM used for the regfiles.
107 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
108 so that the register fields are identical to as if SV was not in effect
109 i.e. under these circumstances (EXTRA=0) the register field names RA,
110 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
111 `scalar identity behaviour` described above.
115 With the way that EXTRA fields are defined and applied to register fields,
116 future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
117 requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
119 # Remapped Encoding (`RM[0:23]`)
121 To allow relatively easy remapping of which portions of the Prefix Opcode
122 Map are used for SVP64 without needing to rewrite a large portion of the
123 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
124 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
127 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
128 is defined in the Prefix Fields section.
130 ## Prefix Opcode Map (64-bit instruction encoding)
132 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
134 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
135 empty spaces are yet-to-be-allocated Illegal Instructions.
137 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
138 |------|--------|--------|--------|--------|--------|--------|--------|--------|
139 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
140 |001---| | | | | | | | |
141 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
142 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
143 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
144 |101---| | | | | | | | |
145 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
146 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
148 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
152 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
153 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
154 This is achieved by setting bits 7 and 9 to 1:
156 | Name | Bits | Value | Description |
157 |------------|---------|-------|--------------------------------|
158 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
159 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
160 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
161 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
162 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
163 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
165 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
168 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
169 |--------|-------|---|-------|---|----------|
170 | EXT01 | RM | 1 | RM | 1 | RM |
171 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
173 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
174 instruction. That instruction becomes "prefixed" with the SVP context: the
175 Remapped Encoding field (RM).
177 It is important to note that unlike v3.1 64-bit prefixed instructions
178 there is insufficient space in `RM` to provide identification of
179 any SVP64 Fields without first partially decoding the
180 32-bit suffix. Extreme caution and care must therefore be taken
181 when extending SVP64 in future, to not create unnecessary relationships
182 between prefix and suffix that could complicate decoding, adding latency.
186 The following fields are common to all Remapped Encodings:
188 | Field Name | Field bits | Description |
189 |------------|------------|----------------------------------------|
190 | MASKMODE | `0` | Execution (predication) Mask Kind |
191 | MASK | `1:3` | Execution Mask |
192 | ELWIDTH | `4:5` | Element Width |
193 | ELWIDTH_SRC | `6:7` | Element Width for Source |
194 | SUBVL | `8:9` | Sub-vector length |
195 | MODE | `19:23` | changes Vector behaviour |
197 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
198 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
199 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
200 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
202 Bits 10 to 18 are further decoded depending on RM category for the instruction.
203 Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
205 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
209 Mode is an augmentation of SV behaviour. Different types of
210 instructions have different needs, similar to Power ISA
211 v3.1 64 bit prefix 8LS and MTRR formats apply to different
212 instruction types. Modes include Reduction, Iteration, arithmetic
213 saturation, and Fail-First. More specific details in each
214 section and in the [[svp64/appendix]]
216 * For condition register operations see [[sv/cr_ops]]
217 * For LD/ST Modes, see [[sv/ldst]].
218 * For Branch modes, see [[sv/branches]]
219 * For arithmetic and logical, see [[sv/normal]]
223 Default behaviour is set to 0b00 so that zeros follow the convention of
224 `scalar identity behaviour`. In this case it means that elwidth overrides
225 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
226 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
227 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
228 states that, again, the behaviour is not to be modified.
230 Only when elwidth is nonzero is the element width overridden to the
231 explicitly required value.
233 ## Elwidth for Integers:
235 | Value | Mnemonic | Description |
236 |-------|----------------|------------------------------------|
237 | 00 | DEFAULT | default behaviour for operation |
238 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
239 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
240 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
242 This encoding is chosen such that the byte width may be computed as `(3-ew)<<8`
244 ## Elwidth for FP Registers:
246 | Value | Mnemonic | Description |
247 |-------|----------------|------------------------------------|
248 | 00 | DEFAULT | default behaviour for FP operation |
249 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
250 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
251 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
254 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
255 is reserved for a future implementation of SV
257 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
258 perform its operation at **half** the ELWIDTH then padded back out
259 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
260 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
261 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
266 Element-width overrides for CR Fields has no meaning. The bits
267 are therefore used for other purposes, or when Rc=1, the Elwidth
268 applies to the result being tested, but not to the Vector of CR Fields.
273 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
274 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
275 lines up in combination with all other "default is all zeros" behaviour.
277 | Value | Mnemonic | Subvec | Description |
278 |-------|-----------|---------|------------------------|
279 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
280 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
281 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
282 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
284 The SUBVL encoding value may be thought of as an inclusive range of a
285 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
286 this may be considered to be elements 0b00 to 0b01 inclusive.
288 # MASK/MASK_SRC & MASKMODE Encoding
290 TODO: rename MASK_KIND to MASKMODE
292 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
293 types may not be mixed.
295 Special note: to disable predication this field must
296 be set to zero in combination with Integer Predication also being set
297 to 0b000. this has the effect of enabling "all 1s" in the predicate
298 mask, which is equivalent to "not having any predication at all"
299 and consequently, in combination with all other default zeros, fully
300 disables SV (`scalar identity behaviour`).
302 `MASKMODE` may be set to one of 2 values:
304 | Value | Description |
305 |-----------|------------------------------------------------------|
306 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
307 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
309 Integer Twin predication has a second set of 3 bits that uses the same
310 encoding thus allowing either the same register (r3 or r10) to be used
311 for both src and dest, or different regs (one for src, one for dest).
313 Likewise CR based twin predication has a second set of 3 bits, allowing
314 a different test to be applied.
316 Note that it is assumed that Predicate Masks (whether INT or CR)
317 are read *before* the operations proceed. In practice (for CR Fields)
318 this creates an unnecessary block on parallelism. Therefore,
319 it is up to the programmer to ensure that the CR fields used as
320 Predicate Masks are not being written to by any parallel Vector Loop.
321 Doing so results in **UNDEFINED** behaviour, according to the definition
322 outlined in the OpenPOWER v3.0B Specification.
324 Hardware Implementations are therefore free and clear to delay reading
325 of individual CR fields until the actual predicated element operation
326 needs to take place, safe in the knowledge that no programmer will
327 have issued a Vector Instruction where previous elements could have
328 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
330 ## Integer Predication (MASKMODE=0)
332 When the predicate mode bit is zero the 3 bits are interpreted as below.
333 Twin predication has an identical 3 bit field similarly encoded.
335 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
337 | Value | Mnemonic | Element `i` enabled if: |
338 |-------|----------|------------------------------|
339 | 000 | ALWAYS | predicate effectively all 1s |
340 | 001 | 1 << R3 | `i == R3` |
341 | 010 | R3 | `R3 & (1 << i)` is non-zero |
342 | 011 | ~R3 | `R3 & (1 << i)` is zero |
343 | 100 | R10 | `R10 & (1 << i)` is non-zero |
344 | 101 | ~R10 | `R10 & (1 << i)` is zero |
345 | 110 | R30 | `R30 & (1 << i)` is non-zero |
346 | 111 | ~R30 | `R30 & (1 << i)` is zero |
348 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
350 ## CR-based Predication (MASKMODE=1)
352 When the predicate mode bit is one the 3 bits are interpreted as below.
353 Twin predication has an identical 3 bit field similarly encoded.
355 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
357 | Value | Mnemonic | Element `i` is enabled if |
358 |-------|----------|--------------------------|
359 | 000 | lt | `CR[offs+i].LT` is set |
360 | 001 | nl/ge | `CR[offs+i].LT` is clear |
361 | 010 | gt | `CR[offs+i].GT` is set |
362 | 011 | ng/le | `CR[offs+i].GT` is clear |
363 | 100 | eq | `CR[offs+i].EQ` is set |
364 | 101 | ne | `CR[offs+i].EQ` is clear |
365 | 110 | so/un | `CR[offs+i].FU` is set |
366 | 111 | ns/nu | `CR[offs+i].FU` is clear |
368 CR based predication. TODO: select alternate CR for twin predication? see
369 [[discussion]] Overlap of the two CR based predicates must be taken
370 into account, so the starting point for one of them must be suitably
371 high, or accept that for twin predication VL must not exceed the range
372 where overlap will occur, *or* that they use the same starting point
373 but select different *bits* of the same CRs
375 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
377 Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs.
379 # Extra Remapped Encoding
381 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
383 There are two categories: Single and Twin Predication.
384 Due to space considerations further subdivision of Single Predication
385 is based on whether the number of src operands is 2 or 3.
387 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
388 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
389 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
390 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
391 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
395 | Field Name | Field bits | Description |
396 |------------|------------|----------------------------------------|
397 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
398 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
399 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
400 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
401 | reserved | `18` | reserved |
405 | Field Name | Field bits | Description |
406 |------------|------------|-------------------------------------------|
407 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
408 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
409 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
411 These are for 2 operand 1 dest instructions, such as `add RT, RA,
412 RB`. However also included are unusual instructions with an implicit dest
413 that is identical to its src reg, such as `rlwinmi`.
415 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
416 an alternative destination. With SV however this becomes possible.
417 Therefore, the fact that the dest is implicitly also a src should not
418 mislead: due to the *prefix* they are different SV regs.
420 * `rlwimi RA, RS, ...`
421 * Rsrc1_EXTRA3 applies to RS as the first src
422 * Rsrc2_EXTRA3 applies to RA as the secomd src
423 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
425 With the addition of the EXTRA bits, the three registers
426 each may be *independently* made vector or scalar, and be independently
427 augmented to 7 bits in length.
431 | Field Name | Field bits | Description |
432 |------------|------------|----------------------------|
433 | Rdest_EXTRA3 | `10:12` | extends Rdest |
434 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
435 | MASK_SRC | `16:18` | Execution Mask for Source |
437 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
441 single-predicate, three registers (2 read, 1 write)
443 | Field Name | Field bits | Description |
444 |------------|------------|----------------------------|
445 | Rdest_EXTRA3 | `10:12` | extends Rdest |
446 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
447 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
449 ## RM-2P-2S1D/1S2D/3S
451 The primary purpose for this encoding is for Twin Predication on LOAD
452 and STORE operations. see [[sv/ldst]] for detailed anslysis.
456 | Field Name | Field bits | Description |
457 |------------|------------|----------------------------|
458 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
459 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
460 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
461 | MASK_SRC | `16:18` | Execution Mask for Source |
463 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
464 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
466 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
468 Note also that LD with update indexed, which takes 2 src and 2 dest
469 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
470 Twin Predication. therefore these are treated as RM-2P-2S1D and the
471 src spec for RA is also used for the same RA as a dest.
473 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
477 EXTRA is the means by which two things are achieved:
479 1. Registers are marked as either Vector *or Scalar*
480 2. Register field numbers (limited typically to 5 bit)
481 are extended in range, both for Scalar and Vector.
483 The register files are therefore extended:
485 * INT is extended from r0-31 to 128
486 * FP is extended from fp0-32 to 128
487 * CR is extended from CR0-7 to CR0-127
489 In the following tables register numbers are constructed from the
490 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
491 or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
492 interoperability between prefixing and nonprefixing of scalar registers
493 is direct and convenient (when the EXTRA field is all zeros).
495 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
500 spec = EXTRA2 << 1 # same as EXTRA3, shifted
502 return (RA << 2) | spec[1:2]
504 return (spec[1:2] << 5) | RA
506 Future versions may extend to 256 by shifting Vector numbering up.
507 Scalar will not be altered.
511 alternative which is understandable and, if EXTRA3 is zero, maps to
512 "no effect" (scalar OpenPOWER ISA field naming). also, these are the
513 encodings used in the original SV Prefix scheme. the reason why they
514 were chosen is so that scalar registers in v3.0B and prefixed scalar
515 registers have access to the same 32 registers.
517 Fields are as follows:
520 * Mode: register is tagged as scalar or vector
521 * Range/Inc: the range of registers accessible from this EXTRA
522 encoding, and the "increment" (accessibility). "/4" means
523 that this EXTRA encoding may only give access (starting point)
525 * MSB..LSB: the bit field showing how the register opcode field
526 combines with EXTRA to give (extend) the register number (GPR)
528 | Value | Mode | Range/Inc | 6..0 |
529 |-----------|-------|---------------|---------------------|
530 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
531 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
532 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
533 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
534 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
535 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
536 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
537 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
541 alternative which is understandable and, if EXTRA2 is zero will map to
542 "no effect" i.e Scalar OpenPOWER register naming:
544 | Value | Mode | Range/inc | 6..0 |
545 |-----------|-------|---------------|-----------|
546 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
547 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
548 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
549 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
553 CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
555 Encoding shown MSB down to LSB
557 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
558 |-------|------|---------------|-----------| --------|---------|
559 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
560 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
561 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
562 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
563 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
564 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
565 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
566 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
570 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
572 Encoding shown MSB down to LSB
574 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
575 |-------|--------|----------------|---------|---------|---------|
576 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
577 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
578 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
579 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
583 Now at its own page: [[svp64/appendix]]