1 # SVP64 Zero-Overhead Loop Prefix Subsystem
4 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[Power|openpower]] v3.0B [[ISA|openpower/isa/]].
9 Credits and acknowledgements:
17 * NLnet Foundation, for funding
18 * OpenPOWER Foundation
23 * IBM for the Power ISA itself
28 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
29 * [[svp64/discussion]]
31 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
34 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
35 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
36 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045> External RFC ls010
37 * [[sv/branches]] chapter
47 Simple-V is a type of Vectorisation best described as a "Prefix Loop
48 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and
49 to the 8086 `REP` Prefix instruction. More advanced features are similar
50 to the Z80 `CPIR` instruction. If naively viewed one-dimensionally as an
51 actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
52 Vector instructions on the SFFS Subset and closer to 10 million 64-bit
53 True-Scalable Vector instructions if introduced on VSX. SVP64, the
54 instruction format used by Simple-V, is therefore best viewed as an
55 orthogonal RISC-paradigm "Prefixing" subsystem instead.
57 Except where explicitly stated all bit numbers remain as in the rest of
58 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
59 the left and counting up as you move rightwards to the LSB end). All bit
60 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
61 **All register numbering and element numbering however is LSB0 ordering**
62 which is a different convention from that used elsewhere in the Power ISA.
64 The SVP64 prefix always comes before the suffix in PC order and must be
65 considered an independent "Defined word" that augments the behaviour of
66 the following instruction, but does **not** change the actual Decoding
67 of that following instruction. **All prefixed 32-bit instructions
68 (Defined Words) retain their non-prefixed encoding and definition**.
70 Two apparent exceptions to the above hard rule exist: SV
71 Branch-Conditional operations and LD/ST-update "Post-Increment"
72 Mode. Post-Increment was considered sufficiently high priority
73 (significantly reducing hot-loop instruction count) that one bit in
74 the Prefix is reserved for it (*Note the intention to release that bit
75 and move Post-Increment instructions to EXT2xx, as part of [[ls011]]*).
76 Vectorised Branch-Conditional operations "embed" the original Scalar
77 Branch-Conditional behaviour into a much more advanced variant that is
78 highly suited to High-Performance Computation (HPC), Supercomputing,
79 and parallel GPU Workloads.
81 *Architectural Resource Allocation note: it is prohibited to accept RFCs
82 which fundamentally violate this hard requirement. Under no circumstances
83 must the Suffix space have an alternate instruction encoding allocated
84 within SVP64 that is entirely different from the non-prefixed Defined
85 Word. Hardware Implementors critically rely on this inviolate guarantee
86 to implement High-Performance Multi-Issue micro-architectures that can
87 sustain 100% throughput*
89 Subset implementations in hardware are permitted, as long as certain
90 rules are followed, allowing for full soft-emulation including future
91 revisions. Compliancy Subsets exist to ensure minimum levels of binary
92 interoperability expectations within certain environments. Details in
93 the [[svp64/appendix]].
95 ## SVP64 encoding features
97 A number of features need to be compacted into a very small space of
100 * Independent per-register Scalar/Vector tagging and range extension on
102 * Element width overrides on both source and destination
103 * Predication on both source and destination
104 * Two different sources of predication: INT and CR Fields
105 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
108 Different classes of operations require different formats. The earlier
109 sections cover the common formats and the four separate modes follow:
110 CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
111 and Branch-Conditional.
113 ## Definition of Reserved in this spec.
115 For the new fields added in SVP64, instructions that have any of their
116 fields set to a reserved value must cause an illegal instruction trap,
117 to allow emulation of future instruction sets, or for subsets of SVP64 to
118 be implemented in hardware and the rest emulated. This includes SVP64
119 SPRs: reading or writing values which are not supported in hardware
120 must also raise illegal instruction traps in order to allow emulation.
121 Unless otherwise stated, reserved values are always all zeros.
123 This is unlike OpenPower ISA v3.1, which in many instances does not
124 require a trap if reserved fields are nonzero. Where the standard Power
125 ISA definition is intended the red keyword `RESERVED` is used.
127 ## Definition of "UnVectoriseable"
129 Any operation that inherently makes no sense if repeated is termed
130 "UnVectoriseable" or "UnVectorised". Examples include `sc` or `sync`
131 which have no registers. `mtmsr` is also classed as UnVectoriseable
132 because there is only one `MSR`.
134 UnVectorised instructions are required to be detected as such if
135 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
138 *Architectural Note: Given that a "pre-classification" Decode Phase is
139 required (identifying whether the Suffix - Defined Word - is
140 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
141 adding "UnVectorised" to this phase is not unreasonable.*
143 ## Definition of Strict Program Order
145 Strict Program Order is defined as giving the appearance, as far
146 as programs are concerned, that instructions were executed
147 strictly in the sequence that they occurred. A "Precise"
149 Micro-architecture goes to considerable lengths to ensure that
152 Many Vector ISAs allow interrupts to occur in the middle of
153 processing of large Vector operations, only under the condition
154 that partial results are cleanly discarded, and continuation on return
155 from the Trap Handler will restart the entire operation.
156 The reason is that saving of full Architectural State is
157 not practical. An example would be a Floating-Point Horizontal Sum instruction
158 (very common in Vector ISAs) or a Dot Product instruction
159 that specifies a higher degree of accuracy for the *internal*
160 accumulator than the registers.
162 Simple-V operates on an entirely different paradigm from traditional
163 Vector ISAs: as a Sub-Program Counter where "Elements" are synonymous
164 with Scalar instructions. With this in mind it is critical for
165 implementations to observe Strict Element-Level Program Order
167 (often simply referred to as just "Strict Program Order"
170 *Any* element is Interruptible and Simple-V has
171 been carefully designed to guarantee that Architectural State may
172 be fully preserved and restored regardless of that same State, but
173 it is not necessarily guaranteed that the amount of time needed to recover
174 will be low latency (particularly if REMAP
177 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
178 but the full SVP64 Architectural State may be saved and
179 restored through manual copying of `SVSTATE` (and the four
180 REMAP SPRs if in use at the time)
181 Whilst this initially sounds unsafe in reality
182 all that Trap Handlers (and function call stack save/restore)
184 use of SVP64 Prefixed instructions to perform the necessary
185 save/restore of Simple-V Architectural State.
186 This capability also allows nested function calls to be made from
187 inside Vertical-First Vector loops, which is very rare for Vector ISAs.
189 Strict Program Order is also preserved by the Parallel Reduction
190 REMAP Schedule, but only at the cost of requiring the destination
191 Vector to be used (Deterministically) to store partial progress of the
194 The only major caveat for REMAP is that
195 after an explicit change to
196 Architectural State caused by writing to the
197 Simple-V SPRs, some implementations may find
198 it easier to take longer to calculate where in a given Schedule
199 the re-mapping Indices were. Obvious examples include Interrupts occuring
200 in the middle of a non-RADIX2 Matrix Multiply Schedule (5x3 by 3x3
202 will force implementations to perform divide and modulo
205 An additional caveat involves Condition Register Fields
206 when also used as Predicate Masks. An operation that
207 overwrites the same CR Fields that are simultaneously
208 being used as a Predicate Mask should exercise extreme care
209 if the overwritten CR field element was needed by a
210 subsequent Element for its Predicate Mask bit.
212 Some implementations may deploy Cray's technique of
213 "Vector Chaining" (including in this case reading the CR field
214 containing the Predicate bit until the very last moment),
215 and consequently avoiding the risk of
216 overwrite is the responsibility of the Programmer.
217 `hphint` may be used here to good effect.
218 Extra Special care is particularly needed here when using REMAP
219 and also Vertical-First Mode.
221 The simplest option is to use Integer Predicate Masks but the
222 caveats are stricter:
224 * In Vertical-First loops Programmers **must not** write to any
225 Integers (r3, r0, r31) used as Predicate Masks. Doing so
226 is `UNDEFINED` behaviour.
227 * An **entire** Vector is held up on Horizontal-First Mode if the
228 Integer Predicate is still in in-flight Reservation Stations
229 or pipelines. Speculative Vector Chained Execution mitigates delays
230 but can be heavy on Reservation Station resources.
232 ## Register files, elements, and Element-width Overrides
234 The relationship between register files, elements, and element-width
235 overrides is expressed as follows:
237 * register files are considered to be *byte-level* contiguous SRAMs,
238 accessed exclusively in Little-Endian Byte-Order at all times
239 * elements are sequential contiguous unbounded arrays starting at the "address"
240 of any given 64-bit GPR or FPR, numbered from 0 as the first,
241 "spilling" into numerically-sequentially-increasing GPRs
242 * element-width overrides set the width of the *elements* in the
243 sequentially-numbered contiguous array.
245 The relationship is best defined in Canonical form, below, in ANSI c as a
246 union data structure. A key difference is that VSR elements are bounded
247 fixed at 128-bit, where SVP64 elements are conceptually unbounded and
248 only limited by the Maximum Vector Length.
250 *Future specification note: SVP64 may be defined on top of VSRs in future.
251 At which point VSX also gains conceptually unbounded VSR register elements*
253 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR
254 Register files are expanded from 32 to 128 entries, and the number of
255 CR Fields expanded from CR0-CR7 to CR0-CR127. (Note: A future version
256 of SVP64 is anticipated to extend the VSR register file).
258 Memory access remains exactly the same: the effects of `MSR.LE` remain
259 exactly the same, affecting as they already do and remain **only**
260 on the Load and Store memory-register operation byte-order, and having
261 nothing to do with the ordering of the contents of register files or
262 register-register arithmetic or logical operations.
264 The only major impact on Arithmetic and Logical operations is that all
265 Scalar operations are defined, where practical and workable, to have
266 three new widths: elwidth=32, elwidth=16, elwidth=8.
268 *Architectural note: a future revision of SVP64 for VSX may have entirely
269 different definitions of possible elwidths.*
272 elwidth=64 is the pre-existing (Scalar) behaviour which remains 100%
273 unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit
274 variant of `addi`, but the sole exclusive difference is the width.
275 *In no way* is the actual `addi` instruction fundamentally altered
276 to become an entirely different operation.
277 FP Operations elwidth overrides are also defined, as explained in
278 the [[svp64/appendix]].
280 To be absolutely clear:
283 There are no conceptual arithmetic ordering or other changes over the
284 Scalar Power ISA definitions to registers or register files or to
285 arithmetic or Logical Operations, beyond element-width subdivision
289 numbering is naturally **LSB0-sequentially-incrementing from zero, not
290 MSB0-incrementing** including when element-width overrides are used,
291 at which point the elements progress through each register
292 sequentially from the LSB end
293 (confusingly numbered the highest in MSB0 ordering) and progress
294 incrementally to the MSB end (confusingly numbered the lowest in
297 When exclusively using MSB0-numbering, SVP64 becomes unnecessarily complex
298 to both express and subsequently understand: the required conditional
299 subtractions from 63, 31, 15 and 7 needed to express the fact that
300 elements are LSB0-sequential unfortunately become a hostile minefield,
301 obscuring both intent and meaning. Therefore for the purposes of this
302 section the more natural **LSB0 numbering is assumed** and it is left
303 to the reader to translate to MSB0 numbering.
305 The Canonical specification for how element-sequential numbering and
306 element-width overrides is defined is expressed in the following c
307 structure, assuming a Little-Endian system, and naturally using LSB0
308 numbering everywhere because the ANSI c specification is inherently LSB0.
309 Note the deliberate similarity to how VSX register elements are defined,
310 from Figure 97, Book I, Section 6.3, Page 258:
315 uint8_t actual_bytes[8];
316 // all of these are very deliberately unbounded arrays
317 // that intentionally "wrap" into subsequent actual_bytes...
318 uint8_t bytes[]; // elwidth 8
319 uint16_t hwords[]; // elwidth 16
320 uint32_t words[]; // elwidth 32
321 uint64_t dwords[]; // elwidth 64
325 // ... here, as packed statically-defined GPRs.
326 elreg_t int_regfile[128];
328 // use element 0 as the destination
329 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
331 case 64: el->dwords[0] = int_regfile[gpr].dwords[element];
332 case 32: el->words[0] = int_regfile[gpr].words[element];
333 case 16: el->hwords[0] = int_regfile[gpr].hwords[element];
334 case 8 : el->bytes[0] = int_regfile[gpr].bytes[element];
338 // use element 0 as the source
339 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
341 case 64: int_regfile[gpr].dwords[element] = el->dwords[0];
342 case 32: int_regfile[gpr].words[element] = el->words[0];
343 case 16: int_regfile[gpr].hwords[element] = el->hwords[0];
344 case 8 : int_regfile[gpr].bytes[element] = el->bytes[0];
349 Example Vector-looped add operation implementation when elwidths are 64-bit:
352 # vector-add RT, RA,RB using the "uint64_t" union member, "dwords"
354 int_regfile[RT].dword[i] = int_regfile[RA].dword[i] + int_regfile[RB].dword[i]
357 However if elwidth overrides are set to 16 for both source and destination:
360 # vector-add RT, RA, RB using the "uint64_t" union member "hwords"
362 int_regfile[RT].hwords[i] = int_regfile[RA].hwords[i] + int_regfile[RB].hwords[i]
365 The most fundamental aspect here to understand is that the wrapping
366 into subsequent Scalar GPRs that occurs on larger-numbered elements
367 including and especially on smaller element widths is **deliberate
368 and intentional**. From this Canonical definition it should be clear
369 that sequential elements begin at the LSB end of any given underlying
370 Scalar GPR, progress to the MSB end, and then to the LSB end of the
371 *next numerically-larger Scalar GPR*. In the example above if VL=5
372 and RT=1 then the contents of GPR(1) and GPR(2) will be as follows.
373 For clarity in the table below:
375 * Both MSB0-ordered bitnumbering *and* LSB-ordered bitnumbering are shown
376 * The GPR-numbering is considered LSB0-ordered
377 * The Element-numbering (result0-result4) is LSB0-ordered
378 * Each of the results (result0-result4) are 16-bit
379 * "same" indicates "no change as a result of the Vectorised add"
382 | MSB0: | 0:15 | 16:31 | 32:47 | 48:63 |
383 | LSB0: | 63:48 | 47:32 | 31:16 | 15:0 |
384 |--------|---------|---------|---------|---------|
385 | GPR(0) | same | same | same | same |
386 | GPR(1) | result3 | result2 | result1 | result0 |
387 | GPR(2) | same | same | same | result4 |
388 | GPR(3) | same | same | same | same |
389 | ... | ... | ... | ... | ... |
390 | ... | ... | ... | ... | ... |
393 Note that the upper 48 bits of GPR(2) would **not** be modified due to
394 the example having VL=5. Thus on "wrapping" - sequential progression
395 from GPR(1) into GPR(2) - the 5th result modifies **only** the bottom
398 If the 16-bit operation were to be followed up with a 32-bit Vectorised
399 Operation, the exact same contents would be viewed as follows:
402 | MSB0: | 0:31 | 32:63 |
403 | LSB0: | 63:32 | 31:0 |
404 |--------|----------------------|----------------------|
405 | GPR(0) | same | same |
406 | GPR(1) | (result3 || result2) | (result1 || result0) |
407 | GPR(2) | same | (same || result4) |
408 | GPR(3) | same | same |
413 In other words, this perspective really is no different from the situation
414 where the actual Register File is treated as an Industry-standard
415 byte-level-addressable Little-Endian-addressed SRAM. Note that
416 this perspective does **not** involve `MSR.LE` in any way shape or
417 form because `MSR.LE` is directly in control of the Memory-to-Register
418 byte-ordering. This section is exclusively about how to correctly perceive
419 Simple-V-Augmented **Register** Files.
421 *Engineering note: to avoid a Read-Modify-Write at the register
422 file it is strongly recommended to implement byte-level write-enable lines
423 exactly as has been implemented in DRAM ICs for many decades. Additionally
424 the predicate mask bit is advised to be associated with the element
425 operation and alongside the result ultimately passed to the register file.
426 When element-width is set to 64-bit the relevant predicate mask bit
427 may be repeated eight times and pull all eight write-port byte-level
428 lines HIGH. Clearly when element-width is set to 8-bit the relevant
429 predicate mask bit corresponds directly with one single byte-level
430 write-enable line. It is up to the Hardware Architect to then amortise
431 (merge) elements together into both PredicatedSIMD Pipelines as well
432 as simultaneous non-overlapping Register File writes, to achieve High
433 Performance designs. Overall it helps to think of the GPR and FPR
434 register files as being much more akin to a 64-bit-wide byte-level-addressable SRAM.*
436 **Comparative equivalent using VSR registers**
438 For a comparative data point the VSR Registers may be expressed in the
439 same fashion. The c code below is directly an expression of Figure 97 in
440 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating
441 for MSB0 numbering in both bits and elements, adapting in full to LSB0
442 numbering, and obeying LE ordering*.
444 **Crucial to understanding why the subtraction from 1,3,7,15 is present is
445 because the Power ISA numbers VSX Registers elements also in MSB0 order**.
446 SVP64 very specifically numbers elements in **LSB0** order with the first
447 element (numbered zero) being at the bitwise-numbered **LSB** end of the
448 register, where VSX does the reverse: places the numerically-*highest*
449 (last-numbered) element at the LSB end of the register.
454 // these do NOT match their Power ISA VSX numbering directly, they are all reversed
455 // bytes[15] is actually VSR.byte[0] for example. if this convention is not
456 // followed then everything ends up in the wrong place
457 uint8_t bytes[16]; // elwidth 8, QTY 16 FIXED total
458 uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total
459 uint32_t words[4]; // elwidth 32, QTY 8 FIXED total
460 uint64_t dwords[2]; // elwidth 64, QTY 2 FIXED total
461 uint8_t actual_bytes[16]; // totals 128-bit
464 elreg_t VSR_regfile[64];
466 static void check_num_elements(int elt, int width) {
468 case 64: assert elt < 2;
469 case 32: assert elt < 4;
470 case 16: assert elt < 8;
471 case 8 : assert elt < 16;
474 void get_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
475 check_num_elements(elt, width);
477 case 64: el->dwords[0] = VSR_regfile[gpr].dwords[1-elt];
478 case 32: el->words[0] = VSR_regfile[gpr].words[3-elt];
479 case 16: el->hwords[0] = VSR_regfile[gpr].hwords[7-elt];
480 case 8 : el->bytes[0] = VSR_regfile[gpr].bytes[15-elt];
483 void set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
484 check_num_elements(elt, width);
486 case 64: VSR_regfile[gpr].dwords[1-elt] = el->dwords[0];
487 case 32: VSR_regfile[gpr].words[3-elt] = el->words[0];
488 case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[0];
489 case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[0];
494 For VSR Registers one key difference is that the overlay of different
495 element widths is clearly a *bounded static quantity*, whereas for
496 Simple-V the elements are unrestrained and permitted to flow into
497 *successive underlying Scalar registers*. This difference is absolutely
498 critical to a full understanding of the entire Simple-V paradigm and
499 why element-ordering, bit-numbering *and register numbering* are all so
502 Implementations are not permitted to violate the Canonical
503 definition. Software will be critically relying on the wrapped (overflow)
504 behaviour inherently implied by the unbounded variable-length c arrays.
506 Illustrating the exact same loop with the exact same effect as achieved
507 by Simple-V we are first forced to create wrapper functions, to cater
508 for the fact that VSR register elements are static bounded:
511 int calc_VSR_reg_offs(int elt, int width) {
513 case 64: return floor(elt / 2);
514 case 32: return floor(elt / 4);
515 case 16: return floor(elt / 8);
516 case 8 : return floor(elt / 16);
519 int calc_VSR_elt_offs(int elt, int width) {
521 case 64: return (elt % 2);
522 case 32: return (elt % 4);
523 case 16: return (elt % 8);
524 case 8 : return (elt % 16);
527 void _set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
528 int new_elt = calc_VSR_elt_offs(elt, width);
529 int new_reg = calc_VSR_reg_offs(elt, width);
530 set_VSR_element(el, gpr+new_reg, new_elt, width);
534 And finally use these functions:
537 # VSX-add RT, RA, RB using the "uint64_t" union member "hwords"
539 el_reg_t result, ra, rb;
540 _get_VSR_element(&ra, RA, i, 16);
541 _get_VSR_element(&rb, RB, i, 16);
542 result.hwords[0] = ra.hwords[0] + rb.hwords[0]; // use array 0 elements
543 _set_VSR_element(&result, RT, i, 16);
547 ## Scalar Identity Behaviour
549 SVP64 is designed so that when the prefix is all zeros, and VL=1, no
550 effect or influence occurs (no augmentation) such that all standard Power
551 ISA v3.0/v3.1 instructions covered by the prefix are "unaltered". This
552 is termed `scalar identity behaviour` (based on the mathematical
553 definition for "identity", as in, "identity matrix" or better "identity
556 Note that this is completely different from when VL=0. VL=0 turns all
557 operations under its influence into `nops` (regardless of the prefix)
558 whereas when VL=1 and the SV prefix is all zeros, the operation simply
559 acts as if SV had not been applied at all to the instruction (an
560 "identity transformation").
562 The fact that `VL` is dynamic and can be set to any value at runtime
563 based on program conditions and behaviour means very specifically that
564 `scalar identity behaviour` is **not** a redundant encoding. If the only
565 means by which VL could be set was by way of static-compiled immediates
566 then this assertion would be false. VL should not be confused with
567 MAXVL when understanding this key aspect of SimpleV.
569 ## Register Naming and size
571 As indicated above SV Registers are simply the GPR, FPR and CR register
572 files extended linearly to larger sizes; SV Vectorisation iterates
573 sequentially through these registers (LSB0 sequential ordering from 0
576 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
577 r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV)
578 as r0 to r127. Likewise FP registers are
579 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
580 CR0 thru CR127. In the Lower SV Compliancy Levels the quantity of registers
581 remains the same in order to reduce implementation cost for Embedded systems.
583 The names of the registers therefore reflects a simple linear extension
584 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
585 would be reflected by a linear increase in the size of the underlying
586 SRAM used for the regfiles.
588 Note: when an EXTRA field (defined below) is zero, SV is deliberately
589 designed so that the register fields are identical to as if SV was not in
590 effect i.e. under these circumstances (EXTRA=0) the register field names
591 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
592 This is part of `scalar identity behaviour` described above.
594 **Condition Register(s)**
596 The Scalar Power ISA Condition Register is a 64 bit register where
597 the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used.
598 This convention is *preserved* in SVP64 and an additional 15 Condition
599 Registers provided in order to store the new CR Fields, CR8-CR15,
600 CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition
601 Register are *also* not used: only the bottom 32 bits (numbered 32:63
604 *Programmer's note: using `sv.mfcr` without element-width overrides
605 to take into account the fact that the top 32 MSBs are zero and thus
606 effectively doubling the number of GPR registers required to hold all 128
607 CR Fields would seem the only option because a source elwidth override
608 to 32-bit would take only the bottom 16 LSBs of the Condition Register
609 and set the top 16 LSBs to zeros. However in this case it
610 is possible to use destination element-width overrides (for `sv.mfcr`.
611 source overrides would be used on the GPR of `sv.mtocrf`), whereupon
612 truncation of the 64-bit Condition Register(s) occurs, throwing away
613 the zeros and storing the remaining (valid, desired) 32-bit values
614 sequentially into (LSB0-convention) lower-numbered and upper-numbered
615 halves of GPRs respectively. The programmer is expected to be aware
616 however that the full width of the entire 64-bit Condition Register
617 is considered to be "an element". This is **not** like any other
618 Condition-Register instructions because all other CR instructions,
619 on closer investigation, will be observed to all be CR-bit or CR-Field
620 related. Thus a `VL` of 16 must be used*
622 **Condition Register Fields as Predicate Masks**
624 Condition Register Fields perform an additional duty in Simple-V: they are
625 used for Predicate Masks. ARM's Scalar Instruction Set calls single-bit
626 predication "Conditional Execution", and utilises Condition Codes for
627 exactly this purpose to solve the problem caused by Branch Speculation.
628 In a Vector ISA context the concept of Predication is naturally extended
629 from single-bit to multi-bit, and the (well-known) benefits become all the
630 more critical given that parallel branches in Vector ISAs are impossible
631 (even a Vector ISA can only have Scalar branches).
633 However the Scalar Power ISA does not have Conditional Execution (for
634 which, if it had ever been considered, Condition Register bits would be
635 a perfect natural fit). Thus, when adding Predication using CR Fields
636 via Simple-V it becomes a somewhat disruptive addition to the Power ISA.
638 To ameliorate this situation, particularly for pre-existing Hardware
639 designs implementing up to Scalar Power ISA v3.1, some rules are set that
640 allow those pre-existing designs not to require heavy modification to
641 their existing Scalar pipelines. These rules effectively allow Hardware
642 Architects to add the additional CR Fields CR8 to CR127 as if they were
643 an **entirely separate register file**.
645 * any instruction involving more than 1 source 1 destination
646 where one of the operands is a Condition Register is prohibited from
647 using registers from both the CR0-7 group and the CR8-127 group at
649 * any instruction involving 1 source 1 destination where either the
650 source or the destination is a Condition Register is prohibited
651 from setting CR0-7 as a Vector.
652 * prohibitions are required to be enforced by raising Illegal Instruction
655 Examples of permitted instructions:
658 sv.crand *cr8.eq, *cr16.le, *cr40.so # all CR8-CR127
659 sv.mfcr cr5, *cr40 # only one source (CR40) copied to CR5
660 sv.mfcr *cr16, cr40 # Vector-Splat CR40 onto CR16,17,18...
661 sv.mfcr *cr16, cr3 # Vector-Splat CR3 onto CR16,17,18...
664 Examples of prohibited instructions:
667 sv.mfcr *cr0, cr40 # Vector-Splat onto CR0,1,2
668 sv.crand cr7, cr9, cr10 # crosses over between CR0-7 and CR8-127
673 With the way that EXTRA fields are defined and applied to register
674 fields, future versions of SV may involve 256 or greater registers
675 in some way as long as the reputation of Power ISA for full backwards
676 binary interoperability is preserved. Backwards binary compatibility
677 may be achieved with a PCR bit (Program Compatibility Register) or an
678 MSR bit analogous to SF. Further discussion is out of scope for this
681 Additionally, a future variant of SVP64 will be applied to the Scalar
682 (Quad-precision and 128-bit) VSX instructions. Element-width overrides are
683 an opportunity to expand a future version of the Power ISA to 256-bit,
684 512-bit and 1024-bit operations, as well as doubling or quadrupling the
685 number of VSX registers to 128 or 256. Again further discussion is out
686 of scope for this version of SVP64.
692 ## SVP64 Remapped Encoding (`RM[0:23]`)
694 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits
695 32-37 are the Primary Opcode of the Suffix "Defined Word". 38-63 are the
696 remainder of the Defined Word. Note that the new EXT232-263 SVP64 area
697 it is obviously mandatory that bit 32 is required to be set to 1.
699 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
700 |-----|---|---|----------|--------|----------|-----------------------|
701 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
702 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
704 It is important to note that unlike EXT1xx 64-bit prefixed instructions
705 there is insufficient space in `RM` to provide identification of
706 any SVP64 Fields without first partially decoding the 32-bit suffix.
707 Similar to the "Forms" (X-Form, D-Form) the `RM` format is individually
708 associated with every instruction. However this still does not adversely
709 affect Multi-Issue Decoding because the identification of the *length*
710 of anything in the 64-bit space has been kept brutally simple (EXT009),
711 and further decoding of any number of 64-bit Encodings in parallel at
712 that point is fully independent.
714 Extreme caution and care must be taken when extending SVP64
715 in future, to not create unnecessary relationships between prefix and
716 suffix that could complicate decoding, adding latency.
720 The following fields are common to all Remapped Encodings:
722 | Field Name | Field bits | Description |
723 |------------|------------|----------------------------------------|
724 | MASKMODE | `0` | Execution (predication) Mask Kind |
725 | MASK | `1:3` | Execution Mask |
726 | SUBVL | `8:9` | Sub-vector length |
728 The following fields are optional or encoded differently depending
729 on context after decoding of the Scalar suffix:
731 | Field Name | Field bits | Description |
732 |------------|------------|----------------------------------------|
733 | ELWIDTH | `4:5` | Element Width |
734 | ELWIDTH_SRC | `6:7` | Element Width for Source |
735 | EXTRA | `10:18` | Register Extra encoding |
736 | MODE | `19:23` | changes Vector behaviour |
738 * MODE changes the behaviour of the SV operation (result saturation,
740 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
741 and Audio/Video DSP work
742 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
744 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
745 sources: scalar INT and Vector CR).
746 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
747 for the instruction, which is determined only by decoding the Scalar 32
750 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
751 such as `RM-1P-3S1D` which indicates for this example that the operation
752 is to be single-predicated and that there are 3 source operand EXTRA
753 tags and one destination operand tag.
755 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
756 or increased latency in some implementations due to lane-crossing.
760 Mode is an augmentation of SV behaviour. Different types of instructions
761 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
762 formats apply to different instruction types. Modes include Reduction,
763 Iteration, arithmetic saturation, and Fail-First. More specific details
764 in each section and in the [[svp64/appendix]]
766 * For condition register operations see [[sv/cr_ops]]
767 * For LD/ST Modes, see [[sv/ldst]].
768 * For Branch modes, see [[sv/branches]]
769 * For arithmetic and logical, see [[sv/normal]]
773 Default behaviour is set to 0b00 so that zeros follow the convention
774 of `scalar identity behaviour`. In this case it means that elwidth
775 overrides are not applicable. Thus if a 32 bit instruction operates
776 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
777 Likewise when a processor is switched from 64 bit to 32 bit mode,
778 `elwidth=0b00` states that, again, the behaviour is not to be modified.
780 Only when elwidth is nonzero is the element width overridden to the
781 explicitly required value.
783 ### Elwidth for Integers:
785 | Value | Mnemonic | Description |
786 |-------|----------------|------------------------------------|
787 | 00 | DEFAULT | default behaviour for operation |
788 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
789 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
790 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
792 This encoding is chosen such that the byte width may be computed as
795 ### Elwidth for FP Registers:
797 | Value | Mnemonic | Description |
798 |-------|----------------|------------------------------------|
799 | 00 | DEFAULT | default behaviour for FP operation |
800 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
801 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
802 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
805 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
806 is reserved for a future implementation of SV
808 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`)
809 shall perform its operation at **half** the ELWIDTH then padded back out
810 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation
811 that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
812 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
813 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
814 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16 or
815 ELWIDTH=bf16 is reserved and must raise an illegal instruction (IEEE754
816 FP8 or BF8 are not defined).
818 ### Elwidth for CRs (no meaning)
820 Element-width overrides for CR Fields has no meaning. The bits
821 are therefore used for other purposes, or when Rc=1, the Elwidth
822 applies to the result being tested (a GPR or FPR), but not to the
827 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
828 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
829 lines up in combination with all other "default is all zeros" behaviour.
831 | Value | Mnemonic | Subvec | Description |
832 |-------|-----------|---------|------------------------|
833 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
834 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
835 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
836 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
838 The SUBVL encoding value may be thought of as an inclusive range of a
839 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
840 this may be considered to be elements 0b00 to 0b01 inclusive.
842 Effectively, SUBVL is like a SIMD multiplier: instead of just 1
843 element operation issued, SUBVL element operations are issued (as an inner loop).
844 The key difference between VL looping and SUBVL looping
845 is that predication bits are applied per
846 **group**, rather than by individual element.
848 Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
850 ## MASK/MASK_SRC & MASKMODE Encoding
852 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
853 types may not be mixed.
855 Special note: to disable predication this field must be set to zero in
856 combination with Integer Predication also being set to 0b000. this has the
857 effect of enabling "all 1s" in the predicate mask, which is equivalent to
858 "not having any predication at all".
860 `MASKMODE` may be set to one of 2 values:
862 | Value | Description |
863 |-----------|------------------------------------------------------|
864 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
865 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
867 Integer Twin predication has a second set of 3 bits that uses the same
868 encoding thus allowing either the same register (r3, r10 or r31) to be
869 used for both src and dest, or different regs (one for src, one for dest).
871 Likewise CR based twin predication has a second set of 3 bits, allowing
872 a different test to be applied.
874 Note that it cannot necessarily be assumed that Predicate Masks
875 (whether INT or CR) are read in full *before* the operations proceed. In practice (for CR Fields)
876 this creates an unnecessary block on parallelism, prohibiting
877 "Vector Chaining". Therefore, it is up
878 to the programmer to ensure that the CR field Elements used as Predicate Masks
879 are not overwritten by any parallel Vector Loop. Doing so results
880 in **UNDEFINED** behaviour, according to the definition outlined in the
881 Power ISA v3.0B Specification.
883 Hardware Implementations are therefore free and clear to delay reading
884 of individual CR fields until the actual predicated element operation
885 needs to take place, safe in the knowledge that no programmer will have
886 issued a Vector Instruction where previous elements could have overwritten
887 (destroyed) not-yet-executed CR-Predicated element operations.
888 This particularly is an issue when using REMAP, as the order in
889 which CR-Field-based Predicate Mask bits could be read on a per-element
890 execution basis could well conflict with the order in which prior
891 elements wrote to the very same CR Field.
893 Additionally Programmers should avoid using r3 r10 or r30
894 as destination registers when these are also used as a Predicate
895 Mask. Doing so is again UNDEFINED behaviour.
897 ### Integer Predication (MASKMODE=0)
899 When the predicate mode bit is zero the 3 bits are interpreted as below.
900 Twin predication has an identical 3 bit field similarly encoded.
902 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
905 | Value | Mnemonic | Element `i` enabled if: |
906 |-------|----------|------------------------------|
907 | 000 | ALWAYS | predicate effectively all 1s |
908 | 001 | 1 << R3 | `i == R3` |
909 | 010 | R3 | `R3 & (1 << i)` is non-zero |
910 | 011 | ~R3 | `R3 & (1 << i)` is zero |
911 | 100 | R10 | `R10 & (1 << i)` is non-zero |
912 | 101 | ~R10 | `R10 & (1 << i)` is zero |
913 | 110 | R30 | `R30 & (1 << i)` is non-zero |
914 | 111 | ~R30 | `R30 & (1 << i)` is zero |
916 r10 and r30 are at the high end of temporary and unused registers,
917 so as not to interfere with register allocation from ABIs.
920 ### CR-based Predication (MASKMODE=1)
922 When the predicate mode bit is one the 3 bits are interpreted as below.
923 Twin predication has an identical 3 bit field similarly encoded.
925 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
928 | Value | Mnemonic | Element `i` is enabled if |
929 |-------|----------|--------------------------|
930 | 000 | lt | `CR[offs+i].LT` is set |
931 | 001 | nl/ge | `CR[offs+i].LT` is clear |
932 | 010 | gt | `CR[offs+i].GT` is set |
933 | 011 | ng/le | `CR[offs+i].GT` is clear |
934 | 100 | eq | `CR[offs+i].EQ` is set |
935 | 101 | ne | `CR[offs+i].EQ` is clear |
936 | 110 | so/un | `CR[offs+i].FU` is set |
937 | 111 | ns/nu | `CR[offs+i].FU` is clear |
939 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised
940 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
942 The CR Predicates chosen must start on a boundary that Vectorised CR
943 operations can access cleanly, in full. With EXTRA2 restricting starting
944 points to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and
945 CR Predicate Masks have to be adapted to fit on these boundaries as well.
947 ## Extra Remapped Encoding <a name="extra_remap"> </a>
949 Shows all instruction-specific fields in the Remapped Encoding
950 `RM[10:18]` for all instruction variants. Note that due to the very
951 tight space, the encoding mode is *not* included in the prefix itself.
952 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
953 on a per-instruction basis, and, like "Forms" are given a designation
954 (below) of the form `RM-nP-nSnD`. The full list of which instructions
955 use which remaps is here [[opcode_regs_deduped]].
957 **Please note the following**:
960 Machine-readable CSV files have been autogenerated which will make the
961 task of creating SV-aware ISA decoders, documentation, assembler tools
962 compiler tools Simulators documentation all aspects of SVP64 easier
963 and less prone to mistakes. Please avoid manual re-creation of
964 information from the written specification wording in this chapter,
965 and use the CSV files or use the Canonical tool which creates the CSV
966 files, named sv_analysis.py. The information contained within
967 sv_analysis.py is considered to be part of this Specification, even
968 encoded as it is in python3.
972 The mappings are part of the SVP64 Specification in exactly the same
973 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
974 will need a corresponding SVP64 Mapping, which can be derived by-rote
975 from examining the Register "Profile" of the instruction.
977 There are two categories: Single and Twin Predication. Due to space
978 considerations further subdivision of Single Predication is based on
979 whether the number of src operands is 2 or 3. With only 9 bits available
980 some compromises have to be made.
982 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
983 instructions (fmadd, isel, madd).
984 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
985 instructions (src1 src2 dest)
986 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
987 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
988 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
992 | Field Name | Field bits | Description |
993 |------------|------------|----------------------------------------|
994 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
995 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
996 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
997 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
998 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
1000 These are for 3 operand in and either 1 or 2 out instructions.
1001 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
1002 such as `maddedu` have an implicit second destination, RS, the
1003 selection of which is determined by bit 18.
1007 | Field Name | Field bits | Description |
1008 |------------|------------|-------------------------------------------|
1009 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
1010 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
1011 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
1013 These are for 2 operand 1 dest instructions, such as `add RT, RA,
1014 RB`. However also included are unusual instructions with an implicit
1015 dest that is identical to its src reg, such as `rlwinmi`.
1017 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
1018 not have sufficient bit fields to allow an alternative destination.
1019 With SV however this becomes possible. Therefore, the fact that the
1020 dest is implicitly also a src should not mislead: due to the *prefix*
1021 they are different SV regs.
1023 * `rlwimi RA, RS, ...`
1024 * Rsrc1_EXTRA3 applies to RS as the first src
1025 * Rsrc2_EXTRA3 applies to RA as the second src
1026 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
1028 With the addition of the EXTRA bits, the three registers
1029 each may be *independently* made vector or scalar, and be independently
1030 augmented to 7 bits in length.
1034 | Field Name | Field bits | Description |
1035 |------------|------------|----------------------------|
1036 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1037 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1038 | MASK_SRC | `16:18` | Execution Mask for Source |
1040 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
1042 | Field Name | Field bits | Description |
1043 |------------|------------|----------------------------|
1044 | Rsrc1_EXTRA3 | `10:12` | extends Rsrc1 |
1045 | Rsrc2_EXTRA3 | `13:15` | extends Rsrc2 |
1046 | MASK_SRC | `16:18` | Execution Mask for Source |
1050 single-predicate, three registers (2 read, 1 write)
1052 | Field Name | Field bits | Description |
1053 |------------|------------|----------------------------|
1054 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1055 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1056 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
1058 ### RM-2P-2S1D/1S2D/3S
1060 The primary purpose for this encoding is for Twin Predication on LOAD
1061 and STORE operations. see [[sv/ldst]] for detailed analysis.
1065 | Field Name | Field bits | Description |
1066 |------------|------------|----------------------------|
1067 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1068 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1069 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1070 | MASK_SRC | `16:18` | Execution Mask for Source |
1074 For RM-2P-1S2D dest2 is in bits 14:15
1076 | Field Name | Field bits | Description |
1077 |------------|------------|----------------------------|
1078 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1079 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1080 | Rdest2_EXTRA2 | `14:15` | extends Rdest22 (R\*\_EXTRA2 Encoding) |
1081 | MASK_SRC | `16:18` | Execution Mask for Source |
1085 Also that for RM-2P-3S (to cover `stdx` etc.) the names are switched to 3 src:
1086 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
1088 | Field Name | Field bits | Description |
1089 |------------|------------|----------------------------|
1090 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1091 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1092 | Rsrc3_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1093 | MASK_SRC | `16:18` | Execution Mask for Source |
1095 Note also that LD with update indexed, which takes 2 src and
1096 creates 2 dest registers (e.g. `lhaux RT,RA,RB`), does not have room
1097 for 4 registers and also Twin Predication. Therefore these are treated as
1098 RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest.
1100 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
1101 or increased latency in some implementations due to lane-crossing.
1105 EXTRA is the means by which two things are achieved:
1107 1. Registers are marked as either Vector *or Scalar*
1108 2. Register field numbers (limited typically to 5 bit)
1109 are extended in range, both for Scalar and Vector.
1111 The register files are therefore extended:
1113 * INT (GPR) is extended from r0-31 to r0-127
1114 * FP (FPR) is extended from fp0-32 to fp0-fp127
1115 * CR Fields are extended from CR0-7 to CR0-127
1117 However due to pressure in `RM.EXTRA` not all these registers
1118 are accessible by all instructions, particularly those with
1119 a large number of operands (`madd`, `isel`).
1121 In the following tables register numbers are constructed from the
1122 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
1123 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
1124 designation for a given instruction. The prefixing is arranged so that
1125 interoperability between prefixing and nonprefixing of scalar registers
1126 is direct and convenient (when the EXTRA field is all zeros).
1128 A pseudocode algorithm explains the relationship, for INT/FP (see
1129 [[svp64/appendix]] for CRs)
1135 spec = EXTRA2 << 1 # same as EXTRA3, shifted
1136 if spec[0]: # vector
1137 return (RA << 2) | spec[1:2]
1139 return (spec[1:2] << 5) | RA
1142 Future versions may extend to 256 by shifting Vector numbering up.
1143 Scalar will not be altered.
1145 Note that in some cases the range of starting points for Vectors
1150 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
1153 Fields are as follows:
1156 * Mode: register is tagged as scalar or vector
1157 * Range/Inc: the range of registers accessible from this EXTRA
1158 encoding, and the "increment" (accessibility). "/4" means
1159 that this EXTRA encoding may only give access (starting point)
1161 * MSB..LSB: the bit field showing how the register opcode field
1162 combines with EXTRA to give (extend) the register number (GPR)
1164 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1166 | Value | Mode | Range/Inc | 6..0 |
1167 |-----------|-------|---------------|---------------------|
1168 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
1169 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
1170 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
1171 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
1172 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
1173 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
1174 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
1175 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
1179 If EXTRA2 is zero will map to "scalar identity behaviour" i.e Scalar
1180 Power ISA register naming:
1182 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1184 | Value | Mode | Range/inc | 6..0 |
1185 |----------|-------|---------------|-----------|
1186 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
1187 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
1188 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
1189 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
1191 **Note that unlike in EXTRA3, in EXTRA2**:
1193 * the GPR Vectors may only start from
1194 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
1195 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
1197 as there is insufficient bits to cover the full range.
1201 CR Field encoding is essentially the same but made more complex due to CRs
1202 being bit-based, because the application of SVP64 element-numbering applies
1203 to the CR *Field* numbering not the CR register *bit* numbering.
1204 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
1205 and Scalars may only go from `CR0, CR1, ... CR31`
1207 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1208 BA ranges are in MSB0.
1210 For a 5-bit operand (BA, BB, BT):
1212 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1213 |-------|------|---------------|-----------| --------|---------|
1214 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1215 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1216 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
1217 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
1218 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1219 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
1220 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1221 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
1223 For a 3-bit operand (e.g. BFA):
1225 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1226 |-------|------|---------------|-----------| --------|
1227 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1228 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1229 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
1230 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
1231 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1232 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
1233 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1234 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
1238 CR encoding is essentially the same but made more complex due to CRs
1239 being bit-based, because the application of SVP64 element-numbering applies
1240 to the CR *Field* numbering not the CR register *bit* numbering.
1241 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
1243 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1244 BA ranges are in MSB0.
1246 For a 5-bit operand (BA, BB, BC):
1248 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1249 |-------|--------|----------------|---------|---------|---------|
1250 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1251 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1252 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1253 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1255 For a 3-bit operand (e.g. BFA):
1257 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1258 |-------|------|---------------|-----------| --------|
1259 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1260 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1261 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1262 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1267 Now at its own page: [[svp64/appendix]]