1 # SVP64 for OpenPOWER ISA v3.0B
3 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
7 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
10 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
11 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
19 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It is best read in conjunction with the [[sv/overview]] which explains the background.
21 The plan is to create an encoding for SVP64, then to create an encoding
22 for SVP48, then to reorganize them both to improve field overlap,
23 reducing the amount of decoder hardware necessary.
25 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
26 and counting up as you move to the LSB end). All bit ranges are inclusive
27 (so `4:6` means bits 4, 5, and 6).
29 64-bit instructions are split into two 32-bit words, the prefix and the
30 suffix. The prefix always comes before the suffix in PC order.
33 |--------|--------------|--------------|
34 | EXT01 | v3.1B Prefix | v3.1B Suffix |
36 svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
38 ## SVP64 encoding features
40 A number of features need to be compacted into a very small space of only 24 bits:
42 * Independent per-register Scalar/Vector tagging and range extension on every register
43 * Element width overrides on both source and destination
44 * Predication on both source and destination
45 * Two different *types* of predication: INT and CR
46 * SV Modes including saturation (for A/V DSP), mapreduce, fail-first and
47 predicate-result mode.
49 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
51 # Definition of Reserved in this spec.
53 For the new fields added in SVP64, instructions that have any of their
54 fields set to a reserved value must cause an illegal instruction trap,
55 to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
57 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
61 SVP64 is designed so that when the prefix is all zeros, and
63 influence occurs (no augmentation) such that all standard OpenPOWER
64 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
66 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
67 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
69 The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
71 # Register Naming and size
73 SV Registers are simply the INT, FP and CR register files extended
74 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
76 Where the integer regfile in standard scalar
77 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
78 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
79 extended to 64 entries, CR0 thru CR63.
81 The names of the registers therefore reflects a simple linear extension
82 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
83 would be reflected by a linear increase in the size of the underlying
84 SRAM used for the regfiles.
86 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
87 so that the register fields are identical to as if SV was not in effect
88 i.e. under these circumstances (EXTRA=0) the register field names RA,
89 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
90 `scalar identity behaviour` described above.
94 With the way that EXTRA fields are defined and applied to register fields,
95 future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
96 requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
98 # Remapped Encoding (`RM[0:23]`)
100 To allow relatively easy remapping of which portions of the Prefix Opcode
101 Map are used for SVP64 without needing to rewrite a large portion of the
102 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
103 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
106 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
107 is defined in the Prefix Fields section.
109 ## Prefix Opcode Map (64-bit instruction encoding)
111 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
113 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
114 empty spaces are yet-to-be-allocated Illegal Instructions.
116 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
117 |------|--------|--------|--------|--------|--------|--------|--------|--------|
118 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
119 |001---| | | | | | | | |
120 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
121 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
122 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
123 |101---| | | | | | | | |
124 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
125 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
127 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
131 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
132 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
133 This is achieved by setting bits 7 and 9 to 1:
135 | Name | Bits | Value | Description |
136 |------------|---------|-------|--------------------------------|
137 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
138 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
139 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
140 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
141 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
142 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
144 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
147 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
148 |--------|-------|---|-------|---|----------|
149 | EXT01 | RM | 1 | RM | 1 | RM |
150 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
152 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
153 instruction. That instruction becomes "prefixed" with the SVP context: the
154 Remapped Encoding field (RM).
158 The following fields are common to all Remapped Encodings:
160 | Field Name | Field bits | Description |
161 |------------|------------|----------------------------------------|
162 | MASK\_KIND | `0` | Execution (predication) Mask Kind |
163 | MASK | `1:3` | Execution Mask |
164 | ELWIDTH | `4:5` | Element Width |
165 | ELWIDTH_SRC | `6:7` | Element Width for Source |
166 | SUBVL | `8:9` | Sub-vector length |
167 | MODE | `19:23` | changes Vector behaviour |
169 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
170 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
171 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
172 * MASK and MASK_KIND provide predication (two types of sources: scalar INT and Vector CR).
174 Bits 10 to 18 are further decoded depending on RM category for the instruction.
175 Similar to OpenPOWER `X-Form` etc. these are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
177 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
181 Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
185 * **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results.
186 * **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria.
187 *VL is altered as a result*.
188 * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping.
189 * **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[appendix]]
190 note that there are comprehensive caveats when using this mode.
191 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details.
193 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
195 The Mode table is laid out as follows:
197 | 0-1 | 2 | 3 4 | description |
198 | --- | --- |---------|-------------------------- |
199 | 00 | 0 | sz dz | normal mode |
200 | 00 | 1 | sz CRM | reduce mode (mapreduce), SUBVL=1 |
201 | 00 | 1 | SVM CRM | subvector reduce mode, SUBVL>1 |
202 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
203 | 01 | inv | sz RC1 | Rc=0: ffirst z/nonz |
204 | 10 | N | sz dz | sat mode: N=0/1 u/s |
205 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
206 | 11 | inv | sz RC1 | Rc=0: pred-result z/nonz |
210 * **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context.
211 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
212 * **CRM** affects the CR on reduce mode when Rc=1
213 * **SVM** sets "subvector" reduce mode
214 * **N** sets signed/unsigned saturation.
215 **RC1** as if Rc=1, stores CRs *but not the result*
219 ffirst LD/ST to multiple pages via a Vectorised base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail. Therefore in these special circumstances requesting ffirst eith a vector base is instead interpreted as element-strided LD/ST. See <https://bugs.libre-soc.org/show_bug.cgi?id=561>
223 Default behaviour is set to 0b00 so that zeros follow the convention of
224 `scalar identity behaviour`. In this case it means that elwidth overrides
225 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
226 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
227 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
228 states that, again, the behaviour is not to be modified.
230 Only when elwidth is nonzero is the element width overridden to the
231 explicitly required value.
233 ## Elwidth for Integers:
235 | Value | Mnemonic | Description |
236 |-------|----------------|------------------------------------|
237 | 00 | DEFAULT | default behaviour for operation |
238 | 01 | `ELWIDTH=b` | Byte: 8-bit integer |
239 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
240 | 11 | `ELWIDTH=w` | Word: 32-bit integer |
242 ## Elwidth for FP Registers:
244 | Value | Mnemonic | Description |
245 |-------|----------------|------------------------------------|
246 | 00 | DEFAULT | default behaviour for FP operation |
247 | 01 | `ELWIDTH=bf16` | Reserved for `bf16` |
248 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
249 | 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
252 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
253 is reserved for a future implementation of SV
257 TODO, important, particularly for crops, mfcr and mtcr, what elwidth
258 even means. instead it may be possible to use the bits as extra indices
259 (add to EXTRA2/3) to access the full 64 CRs at the bit level. TBD, several ideas
261 The actual width of the CRs cannot be altered: they are 4 bit. Also,
262 for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
263 the INT/FP result to which the elwidth override applies, *not* the CR.
264 This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
266 As mentioned TBD, this leaves crops etc. to have a meaning defined for
267 elwidth, because these ops are pure explicit CR based.
269 Examples: mfxm may take the extra bits and use them as extra mask bits.
271 Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review.
275 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
276 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
277 lines up in combination with all other "default is all zeros" behaviour.
279 | Value | Mnemonic | Subvec | Description |
280 |-------|-----------|---------|------------------------|
281 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
282 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
283 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
284 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
286 The SUBVL encoding value may be thought of as an inclusive range of a
287 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
288 this may be considered to be elements 0b00 to 0b01 inclusive.
290 # MASK/MASK_SRC & MASK_KIND Encoding
292 TODO: rename MASK_KIND to MASKMODE
294 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
295 types may not be mixed.
297 Special note: to get default behaviour (SV disabled) this field must
298 be set to zero in combination with Integer Predication also being set
299 to 0b000. this has the effect of enabling "all 1s" in the predicate
300 mask, which is equivalent to "not having any predication at all"
301 and consequently, in combination with all other default zeros, fully
304 | MASK\_KIND Value | Description |
305 |-----------|------------------------------------------------------|
306 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
307 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
309 Integer Twin predication has a second set of 3 bits that uses the same
310 encoding thus allowing either the same register (r3 or r10) to be used
311 for both src and dest, or different regs (one for src, one for dest).
313 Likewise CR based twin predication has a second set of 3 bits, allowing
314 a different test to be applied.
316 ## Integer Predication (MASK_KIND=0)
318 When the predicate mode bit is zero the 3 bits are interpreted as below.
319 Twin predication has an identical 3 bit field similarly encoded.
321 | Value | Mnemonic | Element `i` enabled if: |
322 |-------|----------|------------------------------|
323 | 000 | ALWAYS | predicate effectively all 1s |
324 | 001 | 1 << R3 | `i == R3` |
325 | 010 | R3 | `R3 & (1 << i)` is non-zero |
326 | 011 | ~R3 | `R3 & (1 << i)` is zero |
327 | 100 | R10 | `R10 & (1 << i)` is non-zero |
328 | 101 | ~R10 | `R10 & (1 << i)` is zero |
329 | 110 | R30 | `R30 & (1 << i)` is non-zero |
330 | 111 | ~R30 | `R30 & (1 << i)` is zero |
332 ## CR-based Predication (MASK_KIND=1)
334 When the predicate mode bit is one the 3 bits are interpreted as below.
335 Twin predication has an identical 3 bit field similarly encoded
337 | Value | Mnemonic | Element `i` is enabled if |
338 |-------|----------|--------------------------|
339 | 000 | lt | `CR[offs+i].LT` is set |
340 | 001 | nl/ge | `CR[offs+i].LT` is clear |
341 | 010 | gt | `CR[offs+i].GT` is set |
342 | 011 | ng/le | `CR[offs+i].GT` is clear |
343 | 100 | eq | `CR[offs+i].EQ` is set |
344 | 101 | ne | `CR[offs+i].EQ` is clear |
345 | 110 | so/un | `CR[offs+i].FU` is set |
346 | 111 | ns/nu | `CR[offs+i].FU` is clear |
348 CR based predication. TODO: select alternate CR for twin predication? see
349 [[discussion]] Overlap of the two CR based predicates must be taken
350 into account, so the starting point for one of them must be suitably
351 high, or accept that for twin predication VL must not exceed the range
352 where overlap will occur, *or* that they use the same starting point
353 but select different *bits* of the same CRs
355 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
357 # Extra Remapped Encoding
359 Shows all instruction-specific fields in the Remapped Encoding `RM[8:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
361 There are two categories: Single and Twin Predication.
362 Due to space considerations further subdivision of Single Predication
363 is based on whether the number of src operands is 2 or 3.
365 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
366 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
367 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
368 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
369 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
373 | Field Name | Field bits | Description |
374 |------------|------------|----------------------------------------|
375 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
376 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
377 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
378 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
379 | reserved | `18` | reserved |
383 | Field Name | Field bits | Description |
384 |------------|------------|-------------------------------------------|
385 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
386 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
387 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
389 These are for 2 operand 1 dest instructions, such as `add RT, RA,
390 RB`. However also included are unusual instructions with an implicit dest
391 that is identical to its src reg, such as `rlwinmi`.
393 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
394 an alternative destination. With SV however this becomes possible.
395 Therefore, the fact that the dest is implicitly also a src should not
396 mislead: due to the *prefix* they are different SV regs.
398 * `rlwimi RA, RS, ...`
399 * Rsrc1_EXTRA3 applies to RS as the first src
400 * Rsrc2_EXTRA3 applies to RA as the secomd src
401 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
403 With the addition of the EXTRA bits, the three registers
404 each may be *independently* made vector or scalar, and be independently
405 augmented to 7 bits in length.
409 | Field Name | Field bits | Description |
410 |------------|------------|----------------------------|
411 | Rdest_EXTRA3 | `10:12` | extends Rdest |
412 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
413 | MASK_SRC | `16:18` | Execution Mask for Source |
415 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
417 ## RM-2P-2S1D/1S2D/3S
419 The primary purpose for this encoding is for Twin Predication on LOAD
420 and STORE operations. see [[sv/ldst]] for detailed anslysis.
424 | Field Name | Field bits | Description |
425 |------------|------------|----------------------------|
426 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
427 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
428 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
429 | MASK_SRC | `16:18` | Execution Mask for Source |
431 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
432 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
434 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
436 Note also that LD with update indexed, which takes 2 src and 2 dest
437 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
438 Twin Predication. therefore these are treated as RM-2P-2S1D and the
439 src spec for RA is also used for the same RA as a dest.
441 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
445 EXTRA is the means by which two things are achieved:
447 1. Registers are marked as either Vector *or Scalar*
448 2. Register field numbers (limited typically to 5 bit)
449 are extended in range, both for Scalar and Vector.
451 In the following tables register numbers are constructed from the
452 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
453 or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
454 interoperability between prefixing and nonprefixing of scalar registers
455 is direct and convenient (when the EXTRA field is all zeros).
457 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
462 spec = EXTRA2 << 1 # same as EXTRA3, shifted
464 return (RA << 2) | spec[0:1]
466 return (spec[0:1] << 5) | RA
470 alternative which is understandable and, if EXTRA3 is zero, maps to
471 "no effect" (scalar OpenPOWER ISA field naming). also, these are the
472 encodings used in the original SV Prefix scheme. the reason why they
473 were chosen is so that scalar registers in v3.0B and prefixed scalar
474 registers have access to the same 32 registers.
476 | R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
477 |-----------|-------|---------------|---------------------|
478 | 000 | Scalar | `r0-r31` | `0b00 RA` |
479 | 001 | Scalar | `r32-r63` | `0b01 RA` |
480 | 010 | Scalar | `r64-r95` | `0b10 RA` |
481 | 011 | Scalar | `r96-r127` | `0b11 RA` |
482 | 100 | Vector | `r0-r124` | `RA 0b00` |
483 | 101 | Vector | `r1-r125` | `RA 0b01` |
484 | 110 | Vector | `r2-r126` | `RA 0b10` |
485 | 111 | Vector | `r3-r127` | `RA 0b11` |
489 alternative which is understandable and, if EXTRA2 is zero will map to
490 "no effect" i.e Scalar OpenPOWER register naming:
492 | R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
493 |-----------|-------|---------------|---------------------|
494 | 00 | Scalar | `r0-r31` | `0b00 RA` |
495 | 01 | Scalar | `r32-r63` | `0b01 RA` |
496 | 10 | Vector | `r0-r124` | `RA 0b00` |
497 | 11 | Vector | `r2-r126` | `RA 0b10` |
501 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
503 Encoding shown MSB down to LSB
505 | R\*\_EXTRA3 | Mode | 7..5 | 4..2 | 1..0 |
506 |-------------|------|---------| --------|---------|
507 | 000 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
508 | 001 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
509 | 010 | Scalar | 0b010 | BA[4:2] | BA[1:0] |
510 | 011 | Scalar | 0b011 | BA[4:2] | BA[1:0] |
511 | 100 | Vector | BA[4:2] | 0b000 | BA[1:0] |
512 | 101 | Vector | BA[4:2] | 0b010 | BA[1:0] |
513 | 110 | Vector | BA[4:2] | 0b100 | BA[1:0] |
514 | 111 | Vector | BA[4:2] | 0b110 | BA[1:0] |
518 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
520 Encoding shown MSB down to LSB
522 | R\*\_EXTRA2 | Mode | 7..5 | 4..2 | 1..0 |
523 |-------------|--------|---------|---------|---------|
524 | 00 | Scalar | 0b000 | BA[4:2] | BA[1:0] |
525 | 01 | Scalar | 0b001 | BA[4:2] | BA[1:0] |
526 | 10 | Vector | BA[4:2] | 0b000 | BA[1:0] |
527 | 11 | Vector | BA[4:2] | 0b100 | BA[1:0] |
531 Now at its own page: [[svp64/appendix]]