3 # DRAFT SVP64 for OpenPOWER ISA v3.0B
5 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. It is in Draft Status and
8 will be submitted to the [[!wikipedia OpenPOWER_Foundation]] ISA WG
9 via the External RFC Process.
11 Credits and acknowledgements:
19 * NLnet Foundation, for funding
20 * OpenPOWER Foundation
23 * IBM for the Power ISA itself
27 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
28 * [[svp64/discussion]]
30 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
31 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
41 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
43 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
44 and counting up as you move to the LSB end). All bit ranges are inclusive
45 (so `4:6` means bits 4, 5, and 6).
47 64-bit instructions are split into two 32-bit words, the prefix and the
48 suffix. The prefix always comes before the suffix in PC order.
51 |--------|--------------|--------------|
52 | EXT01 | v3.1 Prefix | v3.1 Suffix |
54 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
56 Subset implementations in hardware are permitted, as long as certain
57 rules are followed, allowing for full soft-emulation including future
58 revisions. Details in the [[svp64/appendix]].
60 ## SVP64 encoding features
62 A number of features need to be compacted into a very small space of only 24 bits:
64 * Independent per-register Scalar/Vector tagging and range extension on every register
65 * Element width overrides on both source and destination
66 * Predication on both source and destination
67 * Two different sources of predication: INT and CR Fields
68 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
69 predicate-result mode.
71 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
73 # Definition of Reserved in this spec.
75 For the new fields added in SVP64, instructions that have any of their
76 fields set to a reserved value must cause an illegal instruction trap,
77 to allow emulation of future instruction sets, or for subsets of SVP64
78 to be implemented in hardware and the rest emulated.
79 This includes SVP64 SPRs: reading or writing values which are not
80 supported in hardware must also raise illegal instruction traps
81 in order to allow emulation.
82 Unless otherwise stated, reserved values are always all zeros.
84 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition
85 is intended the red keyword `RESERVED` is used.
87 # Scalar Identity Behaviour
89 SVP64 is designed so that when the prefix is all zeros, and
91 influence occurs (no augmentation) such that all standard OpenPOWER
92 v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
94 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
95 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
97 # Register Naming and size
99 SV Registers are simply the INT, FP and CR register files extended
100 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
102 Where the integer regfile in standard scalar
103 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
104 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
105 extended to 128 entries, CR0 thru CR127.
107 The names of the registers therefore reflects a simple linear extension
108 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
109 would be reflected by a linear increase in the size of the underlying
110 SRAM used for the regfiles.
112 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
113 so that the register fields are identical to as if SV was not in effect
114 i.e. under these circumstances (EXTRA=0) the register field names RA,
115 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
116 `scalar identity behaviour` described above.
120 With the way that EXTRA fields are defined and applied to register fields,
121 future versions of SV may involve 256 or greater registers. To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
122 requiring additional prefix bits. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Beyond this, further discussion is out of scope for this version of svp64.
124 # Remapped Encoding (`RM[0:23]`)
126 To allow relatively easy remapping of which portions of the Prefix Opcode
127 Map are used for SVP64 without needing to rewrite a large portion of the
128 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
129 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
132 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
133 is defined in the Prefix Fields section.
135 ## Prefix Opcode Map (64-bit instruction encoding)
137 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
139 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
140 empty spaces are yet-to-be-allocated Illegal Instructions.
142 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
143 |------|--------|--------|--------|--------|--------|--------|--------|--------|
144 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
145 |001---| | | | | | | | |
146 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
147 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
148 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
149 |101---| | | | | | | | |
150 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
151 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
153 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
157 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
158 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
159 This is achieved by setting bits 7 and 9 to 1:
161 | Name | Bits | Value | Description |
162 |------------|---------|-------|--------------------------------|
163 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
164 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
165 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
166 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
167 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
168 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
170 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
173 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
174 |--------|-------|---|-------|---|----------|
175 | EXT01 | RM | 1 | RM | 1 | RM |
176 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
178 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
179 instruction. That instruction becomes "prefixed" with the SVP context: the
180 Remapped Encoding field (RM).
182 It is important to note that unlike v3.1 64-bit prefixed instructions
183 there is insufficient space in `RM` to provide identification of
184 any SVP64 Fields without first partially decoding the
185 32-bit suffix. Extreme caution and care must therefore be taken
186 when extending SVP64 in future, to not create unnecessary relationships
187 between prefix and suffix that could complicate decoding, adding latency.
191 The following fields are common to all Remapped Encodings:
193 | Field Name | Field bits | Description |
194 |------------|------------|----------------------------------------|
195 | MASKMODE | `0` | Execution (predication) Mask Kind |
196 | MASK | `1:3` | Execution Mask |
197 | SUBVL | `8:9` | Sub-vector length |
199 The following fields are optional or encoded differently depending
200 on context after decoding of the Scalar suffix:
202 | Field Name | Field bits | Description |
203 |------------|------------|----------------------------------------|
204 | ELWIDTH | `4:5` | Element Width |
205 | ELWIDTH_SRC | `6:7` | Element Width for Source |
206 | EXTRA | `10:18` | Register Extra encoding |
207 | MODE | `19:23` | changes Vector behaviour |
209 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
210 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
211 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
212 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
213 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
215 Similar to OpenPOWER `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
217 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
221 Mode is an augmentation of SV behaviour. Different types of
222 instructions have different needs, similar to Power ISA
223 v3.1 64 bit prefix 8LS and MTRR formats apply to different
224 instruction types. Modes include Reduction, Iteration, arithmetic
225 saturation, and Fail-First. More specific details in each
226 section and in the [[svp64/appendix]]
228 * For condition register operations see [[sv/cr_ops]]
229 * For LD/ST Modes, see [[sv/ldst]].
230 * For Branch modes, see [[sv/branches]]
231 * For arithmetic and logical, see [[sv/normal]]
235 Default behaviour is set to 0b00 so that zeros follow the convention of
236 `scalar identity behaviour`. In this case it means that elwidth overrides
237 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
238 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
239 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
240 states that, again, the behaviour is not to be modified.
242 Only when elwidth is nonzero is the element width overridden to the
243 explicitly required value.
245 ## Elwidth for Integers:
247 | Value | Mnemonic | Description |
248 |-------|----------------|------------------------------------|
249 | 00 | DEFAULT | default behaviour for operation |
250 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
251 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
252 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
254 This encoding is chosen such that the byte width may be computed as `(3-ew)<<8`
256 ## Elwidth for FP Registers:
258 | Value | Mnemonic | Description |
259 |-------|----------------|------------------------------------|
260 | 00 | DEFAULT | default behaviour for FP operation |
261 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
262 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
263 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
266 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
267 is reserved for a future implementation of SV
269 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
270 perform its operation at **half** the ELWIDTH then padded back out
271 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
272 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
273 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
278 Element-width overrides for CR Fields has no meaning. The bits
279 are therefore used for other purposes, or when Rc=1, the Elwidth
280 applies to the result being tested, but not to the Vector of CR Fields.
285 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
286 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
287 lines up in combination with all other "default is all zeros" behaviour.
289 | Value | Mnemonic | Subvec | Description |
290 |-------|-----------|---------|------------------------|
291 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
292 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
293 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
294 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
296 The SUBVL encoding value may be thought of as an inclusive range of a
297 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
298 this may be considered to be elements 0b00 to 0b01 inclusive.
300 # MASK/MASK_SRC & MASKMODE Encoding
302 TODO: rename MASK_KIND to MASKMODE
304 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
305 types may not be mixed.
307 Special note: to disable predication this field must
308 be set to zero in combination with Integer Predication also being set
309 to 0b000. this has the effect of enabling "all 1s" in the predicate
310 mask, which is equivalent to "not having any predication at all"
311 and consequently, in combination with all other default zeros, fully
312 disables SV (`scalar identity behaviour`).
314 `MASKMODE` may be set to one of 2 values:
316 | Value | Description |
317 |-----------|------------------------------------------------------|
318 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
319 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
321 Integer Twin predication has a second set of 3 bits that uses the same
322 encoding thus allowing either the same register (r3 or r10) to be used
323 for both src and dest, or different regs (one for src, one for dest).
325 Likewise CR based twin predication has a second set of 3 bits, allowing
326 a different test to be applied.
328 Note that it is assumed that Predicate Masks (whether INT or CR)
329 are read *before* the operations proceed. In practice (for CR Fields)
330 this creates an unnecessary block on parallelism. Therefore,
331 it is up to the programmer to ensure that the CR fields used as
332 Predicate Masks are not being written to by any parallel Vector Loop.
333 Doing so results in **UNDEFINED** behaviour, according to the definition
334 outlined in the OpenPOWER v3.0B Specification.
336 Hardware Implementations are therefore free and clear to delay reading
337 of individual CR fields until the actual predicated element operation
338 needs to take place, safe in the knowledge that no programmer will
339 have issued a Vector Instruction where previous elements could have
340 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
342 ## Integer Predication (MASKMODE=0)
344 When the predicate mode bit is zero the 3 bits are interpreted as below.
345 Twin predication has an identical 3 bit field similarly encoded.
347 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
349 | Value | Mnemonic | Element `i` enabled if: |
350 |-------|----------|------------------------------|
351 | 000 | ALWAYS | predicate effectively all 1s |
352 | 001 | 1 << R3 | `i == R3` |
353 | 010 | R3 | `R3 & (1 << i)` is non-zero |
354 | 011 | ~R3 | `R3 & (1 << i)` is zero |
355 | 100 | R10 | `R10 & (1 << i)` is non-zero |
356 | 101 | ~R10 | `R10 & (1 << i)` is zero |
357 | 110 | R30 | `R30 & (1 << i)` is non-zero |
358 | 111 | ~R30 | `R30 & (1 << i)` is zero |
360 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
362 ## CR-based Predication (MASKMODE=1)
364 When the predicate mode bit is one the 3 bits are interpreted as below.
365 Twin predication has an identical 3 bit field similarly encoded.
367 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
369 | Value | Mnemonic | Element `i` is enabled if |
370 |-------|----------|--------------------------|
371 | 000 | lt | `CR[offs+i].LT` is set |
372 | 001 | nl/ge | `CR[offs+i].LT` is clear |
373 | 010 | gt | `CR[offs+i].GT` is set |
374 | 011 | ng/le | `CR[offs+i].GT` is clear |
375 | 100 | eq | `CR[offs+i].EQ` is set |
376 | 101 | ne | `CR[offs+i].EQ` is clear |
377 | 110 | so/un | `CR[offs+i].FU` is set |
378 | 111 | ns/nu | `CR[offs+i].FU` is clear |
380 CR based predication. TODO: select alternate CR for twin predication? see
381 [[discussion]] Overlap of the two CR based predicates must be taken
382 into account, so the starting point for one of them must be suitably
383 high, or accept that for twin predication VL must not exceed the range
384 where overlap will occur, *or* that they use the same starting point
385 but select different *bits* of the same CRs
387 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
389 Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do a transfer (v3.0B). Another idea: the DepMatrices treat scalar CRs as one "thing" and treat the Vectors as a completely separate "thing". also: do modulo arithmetic on allocation of CRs.
391 # Extra Remapped Encoding
393 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
395 These mappings are part of the SVP64 Specification in exactly the same
396 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
397 will need a corresponding SVP64 Mapping, which can be derived by-rote
398 from examining the Register "Profile" of the instruction.
400 There are two categories: Single and Twin Predication.
401 Due to space considerations further subdivision of Single Predication
402 is based on whether the number of src operands is 2 or 3. With only
403 9 bits available some compromises have to be made.
405 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
406 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
407 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
408 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
409 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
413 | Field Name | Field bits | Description |
414 |------------|------------|----------------------------------------|
415 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
416 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
417 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
418 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
419 | EXTRA2_MODE | `18` | used by `divmod2du` and `madded` for RS |
421 These are for 3 operand in and either 1 or 2 out instructions.
422 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
423 such as `madded` have an implicit second destination, RS, the
424 selection of which is determined by bit 18.
428 | Field Name | Field bits | Description |
429 |------------|------------|-------------------------------------------|
430 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
431 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
432 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
434 These are for 2 operand 1 dest instructions, such as `add RT, RA,
435 RB`. However also included are unusual instructions with an implicit dest
436 that is identical to its src reg, such as `rlwinmi`.
438 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
439 an alternative destination. With SV however this becomes possible.
440 Therefore, the fact that the dest is implicitly also a src should not
441 mislead: due to the *prefix* they are different SV regs.
443 * `rlwimi RA, RS, ...`
444 * Rsrc1_EXTRA3 applies to RS as the first src
445 * Rsrc2_EXTRA3 applies to RA as the secomd src
446 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
448 With the addition of the EXTRA bits, the three registers
449 each may be *independently* made vector or scalar, and be independently
450 augmented to 7 bits in length.
454 | Field Name | Field bits | Description |
455 |------------|------------|----------------------------|
456 | Rdest_EXTRA3 | `10:12` | extends Rdest |
457 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
458 | MASK_SRC | `16:18` | Execution Mask for Source |
460 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
464 single-predicate, three registers (2 read, 1 write)
466 | Field Name | Field bits | Description |
467 |------------|------------|----------------------------|
468 | Rdest_EXTRA3 | `10:12` | extends Rdest |
469 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
470 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
472 ## RM-2P-2S1D/1S2D/3S
474 The primary purpose for this encoding is for Twin Predication on LOAD
475 and STORE operations. see [[sv/ldst]] for detailed anslysis.
479 | Field Name | Field bits | Description |
480 |------------|------------|----------------------------|
481 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
482 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
483 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
484 | MASK_SRC | `16:18` | Execution Mask for Source |
486 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
487 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
489 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
491 Note also that LD with update indexed, which takes 2 src and 2 dest
492 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
493 Twin Predication. therefore these are treated as RM-2P-2S1D and the
494 src spec for RA is also used for the same RA as a dest.
496 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
500 EXTRA is the means by which two things are achieved:
502 1. Registers are marked as either Vector *or Scalar*
503 2. Register field numbers (limited typically to 5 bit)
504 are extended in range, both for Scalar and Vector.
506 The register files are therefore extended:
508 * INT is extended from r0-31 to r0-127
509 * FP is extended from fp0-32 to fp0-fp127
510 * CR Fields are extended from CR0-7 to CR0-127
512 In the following tables register numbers are constructed from the
513 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
514 or EXTRA3 field from the SV Prefix. The prefixing is arranged so that
515 interoperability between prefixing and nonprefixing of scalar registers
516 is direct and convenient (when the EXTRA field is all zeros).
518 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
523 spec = EXTRA2 << 1 # same as EXTRA3, shifted
525 return (RA << 2) | spec[1:2]
527 return (spec[1:2] << 5) | RA
529 Future versions may extend to 256 by shifting Vector numbering up.
530 Scalar will not be altered.
534 alternative which is understandable and, if EXTRA3 is zero, maps to
535 "no effect" (scalar OpenPOWER ISA field naming). also, these are the
536 encodings used in the original SV Prefix scheme. the reason why they
537 were chosen is so that scalar registers in v3.0B and prefixed scalar
538 registers have access to the same 32 registers.
540 Fields are as follows:
543 * Mode: register is tagged as scalar or vector
544 * Range/Inc: the range of registers accessible from this EXTRA
545 encoding, and the "increment" (accessibility). "/4" means
546 that this EXTRA encoding may only give access (starting point)
548 * MSB..LSB: the bit field showing how the register opcode field
549 combines with EXTRA to give (extend) the register number (GPR)
551 | Value | Mode | Range/Inc | 6..0 |
552 |-----------|-------|---------------|---------------------|
553 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
554 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
555 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
556 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
557 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
558 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
559 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
560 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
564 alternative which is understandable and, if EXTRA2 is zero will map to
565 "no effect" i.e Scalar OpenPOWER register naming:
567 | Value | Mode | Range/inc | 6..0 |
568 |-----------|-------|---------------|-----------|
569 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
570 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
571 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
572 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
576 CR encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
578 Encoding shown MSB down to LSB
580 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
581 |-------|------|---------------|-----------| --------|---------|
582 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
583 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
584 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
585 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
586 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
587 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
588 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
589 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
593 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
595 Encoding shown MSB down to LSB
597 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
598 |-------|--------|----------------|---------|---------|---------|
599 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
600 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
601 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
602 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
606 Now at its own page: [[svp64/appendix]]