openpower/sv/svp64.mdwn

   1 # SVP64 for OpenPOWER ISA v3.0B
   2
   3 This document describes SV augmentation of the OpenPOWER v3.0B ISA. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the OpenPOWER Foundation (only v3.0B)
   4
   5 Links:
   6
   7 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
   8 * [[svp64/discussion]]
   9 * [[svp64/appendix]]
  10 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
  11 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
  12
  13 Table of contents
  14
  15 [[!toc]]
  16
  17 # Introduction
  18
  19 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It it best read in conjunction with the [[sv/overview]] which explains the background.
  20
  21 The plan is to create an encoding for SVP64, then to create an encoding
  22 for SVP48, then to reorganize them both to improve field overlap,
  23 reducing the amount of decoder hardware necessary.
  24
  25 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
  26 and counting up as you move to the LSB end). All bit ranges are inclusive
  27 (so `4:6` means bits 4, 5, and 6).
  28
  29 64-bit instructions are split into two 32-bit words, the prefix and the
  30 suffix. The prefix always comes before the suffix in PC order.
  31
  32 | 0:5    | 6:31         | 0:31         |
  33 |--------|--------------|--------------|
  34 | EXT01  | v3.1B Prefix | v3.1B Suffix |
  35
  36 svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions  to co-exist in the same binary without conflict.
  37
  38 # Definition of Reserved in this spec.
  39
  40 For the new fields added in SVP64, instructions that have any of their
  41 fields set to a reserved value must cause an illegal instruction trap,
  42 to allow emulation of future instruction sets.
  43
  44 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
  45
  46 # Identity Behaviour
  47
  48 SVP64 is designed so that when the prefix is all zeros, and
  49  VL=1, no effect or
  50 influence occurs (no augmentation) such that all standard OpenPOWER
  51 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
  52
  53 Note that this is completely different from when VL=0.  VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
  54  whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction  (an "identity operation").
  55
  56 The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
  57
  58 # Register Naming and size
  59
  60 SV Registers are simply the INT, FP and CR register files extended
  61 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
  62
  63 Where the integer regfile in standard scalar
  64 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
  65 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
  66 extended to 64 entries, CR0 thru CR63.
  67
  68 The names of the registers therefore reflects a simple linear extension
  69 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
  70 would be reflected by a linear increase in the size of the underlying
  71 SRAM used for the regfiles.
  72
  73 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
  74 so that the register fields are identical to as if SV was not in effect
  75 i.e. under these circumstances (EXTRA=0) the register field names RA,
  76 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.  This is part of
  77 `scalar identity behaviour` described above.
  78
  79 ## Future expansion.
  80
  81 With the way that EXTRA fields are defined and applied to register fields,
  82 future versions of SV may involve 256 or greater registers.  To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
  83 requiring additional prefix bits.  Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register).  Beyond this, further discussion is out of scope for this version of svp64.
  84
  85 # Remapped Encoding (`RM[0:23]`)
  86
  87 To allow relatively easy remapping of which portions of the Prefix Opcode
  88 Map are used for SVP64 without needing to rewrite a large portion of the
  89 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
  90 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
  91 at the LSB.
  92
  93 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
  94 is defined in the Prefix Fields section.
  95
  96 ## Prefix Opcode Map (64-bit instruction encoding)
  97
  98 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
  99
 100 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
 101 empty spaces are yet-to-be-allocated Illegal Instructions.
 102
 103 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
 104 |------|--------|--------|--------|--------|--------|--------|--------|--------|
 105 |000---| 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    |
 106 |001---|        |        |        |        |        |        |        |        |
 107 |010---| 8RR    |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 108 |011---|        |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 109 |100---| MLS    | MLS    | MLS    | MLS    | MLS    | MLS    | MLS    | MLS    |
 110 |101---|        |        |        |        |        |        |        |        |
 111 |110---| MRR    |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 112 |111---|        | MMIRR  |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 113
 114 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
 115
 116 ## Prefix Fields
 117
 118 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
 119 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
 120 This is achieved by setting bits 7 and 9 to 1:
 121
 122 | Name       | Bits    | Value | Description                    |
 123 |------------|---------|-------|--------------------------------|
 124 | EXT01      | `0:5`   | `1`   | Indicates Prefixed 64-bit      |
 125 | `RM[0]`    | `6`     |       | Bit 0 of Remapped Encoding     |
 126 | SVP64_7    | `7`     | `1`   | Indicates this is SVP64        |
 127 | `RM[1]`    | `8`     |       | Bit 1 of Remapped Encoding     |
 128 | SVP64_9    | `9`     | `1`   | Indicates this is SVP64        |
 129 | `RM[2:23]` | `10:31` |       | Bits 2-23 of Remapped Encoding |
 130
 131 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
 132 are constructed:
 133
 134 | 0:5    | 6     | 7 | 8     | 9 | 10:31    |
 135 |--------|-------|---|-------|---|----------|
 136 | EXT01  | RM    | 1 | RM    | 1 | RM       |
 137 | 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
 138
 139 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
 140 instruction.  That instruction becomes "prefixed" with the SVP context: the
 141 Remapped Encoding field (RM).
 142
 143 # Remapped Encoding Fields
 144
 145 Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
 146 variants.  There are two categories:  Single and Twin Predication.
 147 Due to space considerations further subdivision of Single Predication
 148 is based on whether the number of src operands is 2 or 3.
 149
 150 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
 151 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
 152 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
 153 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
 154 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
 155
 156 ## Common RM fields
 157
 158 The following fields are common to all Remapped Encodings:
 159
 160
 161 | Field Name | Field bits | Description                            |
 162 |------------|------------|----------------------------------------|
 163 | MASK\_KIND    | `0`        | Execution (predication) Mask Kind                 |
 164 | MASK          | `1:3`      | Execution Mask                      |
 165 | ELWIDTH       | `4:5`      | Element Width                       |
 166 | SUBVL         | `6:7`      | Sub-vector length                   |
 167 | MODE          | `19:23` | changes Vector behaviour               |
 168
 169 Bits 9 to 18 are further decoded depending on RM category for the instruction.
 170
 171 ## RM-1P-3S1D
 172
 173 | Field Name | Field bits | Description                            |
 174 |------------|------------|----------------------------------------|
 175 | Rdest\_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 176 | Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 177 | Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 178 | Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding)   |
 179 | reserved      | `16`    | reserved                               |
 180
 181 ## RM-1P-2S1D
 182
 183 | Field Name | Field bits | Description                               |
 184 |------------|------------|-------------------------------------------|
 185 | Rdest\_EXTRA3 | `8:10`  | extends Rdest  |
 186 | Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1  |
 187 | Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3    |
 188 | ELWIDTH_SRC   | `17:18` | Element Width for Source      |
 189
 190 These are for 2 operand 1 dest instructions, such as `add RT, RA,
 191 RB`. However also included are unusual instructions with an implicit dest
 192 that is identical to its src reg, such as `rlwinmi`.
 193
 194 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
 195 an alternative destination.  With SV however this becomes possible.
 196 Therefore, the fact that the dest is implicitly also a src should not
 197 mislead: due to the *prefix* they are different SV regs.
 198
 199 * `rlwimi RA, RS, ...`
 200 * Rsrc1_EXTRA3 applies to RS as the first src
 201 * Rsrc2_EXTRA3 applies to RA as the secomd src
 202 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
 203
 204 With the addition of the EXTRA bits, the three registers
 205 each may be *independently* made vector or scalar, and be independently
 206 augmented to 7 bits in length.
 207
 208 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 209
 210 ## RM-2P-1S1D/2S
 211
 212 | Field Name | Field bits | Description                 |
 213 |------------|------------|----------------------------|
 214 | Rdest_EXTRA3 | `8:10`     | extends Rdest             |
 215 | Rsrc1_EXTRA3 | `11:13`    | extends Rsrc1             |
 216 | MASK_SRC     | `14:16`    | Execution Mask for Source |
 217 | ELWIDTH_SRC  | `17:18`    | Element Width for Source  |
 218
 219 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 220
 221 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 222
 223 ## RM-2P-2S1D/1S2D/3S
 224
 225 The primary purpose for this encoding is for Twin Predication on LOAD
 226 and STORE operations.  see [[sv/ldst]] for detailed anslysis.
 227
 228 RM-2P-2S1D:
 229
 230 | Field Name | Field bits | Description                     |
 231 |------------|------------|----------------------------|
 232 | Rdest_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 233 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 234 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 235 | MASK_SRC     | `14:16`    | Execution Mask for Source     |
 236 | ELWIDTH_SRC  | `17:18`    | Element Width for Source      |
 237
 238 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
 239 is in bits 8:9, Rdest1_EXTRA2 in 10:11)
 240
 241 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
 242
 243 Note also that LD with update indexed, which takes 2 src and 2 dest
 244 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
 245 Twin Predication.  therefore these are treated as RM-2P-2S1D and the
 246 src spec for RA is also used for the same RA as a dest.
 247
 248 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 249
 250 # Mode
 251
 252 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 253
 254 These are the modes:
 255
 256 * **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
 257 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.
 258   *VL is altered as a result*.
 259 * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
 260 * **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see separate section below.
 261   note that there are comprehensive caveats when using this mode.
 262 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  This scheme does not apply to crops (crand, cror).  See appendix for details.
 263
 264 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL.
 265
 266 The Mode table is laid out as follows:
 267
 268 | 0-1 |  2  |  3   4  |  description              |
 269 | --- | --- |---------|-------------------------- |
 270 | 00  |   0 |  sz  dz | normal mode                      |
 271 | 00  |   1 | sz CRM  | reduce mode (mapreduce), SUBVL=1 |
 272 | 00  |   1 | SVM CRM | subvector reduce mode, SUBVL>1   |
 273 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 274 | 01  | inv | sz  RC1 |  Rc=0: ffirst z/nonz |
 275 | 10  |   N | sz   dz |  sat mode: N=0/1 u/s |
 276 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 277 | 11  | inv | sz  RC1 |  Rc=0: pred-result z/nonz |
 278
 279 Fields:
 280
 281 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
 282 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 283 * **CRM** affects the CR on reduce mode when Rc=1
 284 * **SVM** sets "subvector" reduce mode
 285 * **N** sets signed/unsigned saturation.
 286 **RC1** as if Rc=1, stores CRs *but not the result*
 287
 288 # R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
 289
 290 EXTRA is the means by which two things are achieved:
 291
 292 1. Registers are marked as either Vector *or Scalar*
 293 2. Register field numbers (limited typically to 5 bit)
 294    are extended in range, both for Scalar and Vector.
 295
 296 In the following tables register numbers are constructed from the
 297 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
 298 or EXTRA3 field from the SV Prefix.  The prefixing is arranged so that
 299 interoperability between prefixing and nonprefixing of scalar registers
 300 is direct and convenient (when the EXTRA field is all zeros).
 301
 302 A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
 303
 304     if extra3_mode:
 305         spec = EXTRA3
 306     else:
 307         spec = EXTRA2 << 1 # same as EXTRA3, shifted
 308     if spec[2]: # vector
 309          return (RA << 2) | spec[0:1]
 310     else:         # scalar
 311          return (spec[0:1] << 5) | RA
 312
 313 ## INT/FP EXTRA3
 314
 315 alternative which is understandable and, if EXTRA3 is zero, maps to
 316 "no effect" (scalar OpenPOWER ISA field naming).  also, these are the
 317 encodings used in the original SV Prefix scheme.  the reason why they
 318 were chosen is so that scalar registers in v3.0B and prefixed scalar
 319 registers have access to the same 32 registers.
 320
 321 | R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
 322 |-----------|-------|---------------|---------------------|
 323 | 000       | Scalar | `r0-r31` | `0b00 RA`      |
 324 | 001       | Scalar | `r32-r63` | `0b01 RA`      |
 325 | 010       | Scalar | `r64-r95` | `0b10 RA`      |
 326 | 011       | Scalar | `r96-r127` | `0b11 RA`      |
 327 | 100       | Vector | `r0-r124` | `RA 0b00`      |
 328 | 101       | Vector | `r1-r125` | `RA 0b01`      |
 329 | 110       | Vector | `r2-r126` | `RA 0b10`      |
 330 | 111       | Vector | `r3-r127` | `RA 0b11`      |
 331
 332 ## INT/FP EXTRA2
 333
 334 alternative which is understandable and, if EXTRA2 is zero will map to
 335 "no effect" i.e Scalar OpenPOWER register naming:
 336
 337 | R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
 338 |-----------|-------|---------------|---------------------|
 339 | 00       | Scalar | `r0-r31` | `0b00 RA`                |
 340 | 01       | Scalar | `r32-r63` | `0b01 RA`      |
 341 | 10       | Vector | `r0-r124` | `RA 0b00`      |
 342 | 11       | Vector | `r2-r126` | `RA 0b10`   |
 343
 344 ## CR EXTRA3
 345
 346 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
 347
 348  Encoding shown MSB down to LSB
 349
 350 | R\*\_EXTRA3 | Mode | 7..5    | 4..2    | 1..0    |
 351 |-------------|------|---------| --------|---------|
 352 | 000       | Scalar | 0b000   | BA[4:2] | BA[1:0] |
 353 | 001       | Scalar | 0b001   | BA[4:2] | BA[1:0] |
 354 | 010       | Scalar | 0b010   | BA[4:2] | BA[1:0] |
 355 | 011       | Scalar | 0b011   | BA[4:2] | BA[1:0] |
 356 | 100       | Vector | BA[4:2] | 0b000   | BA[1:0] |
 357 | 101       | Vector | BA[4:2] | 0b010   | BA[1:0] |
 358 | 110       | Vector | BA[4:2] | 0b100   | BA[1:0] |
 359 | 111       | Vector | BA[4:2] | 0b110   | BA[1:0] |
 360
 361 ## CR EXTRA2
 362
 363 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
 364
 365 Encoding shown MSB down to LSB
 366
 367 | R\*\_EXTRA2 | Mode   | 7..5    | 4..2    | 1..0    |
 368 |-------------|--------|---------|---------|---------|
 369 | 00          | Scalar | 0b000   | BA[4:2] | BA[1:0] |
 370 | 01          | Scalar | 0b001   | BA[4:2] | BA[1:0] |
 371 | 10          | Vector | BA[4:2] | 0b000   | BA[1:0] |
 372 | 11          | Vector | BA[4:2] | 0b100   | BA[1:0] |
 373
 374 # ELWIDTH Encoding
 375
 376 Default behaviour is set to 0b00 so that zeros follow the convention of
 377 "npt doing anything".  In this case it means that elwidth overrides
 378 are not applicable.  Thus if a 32 bit instruction operates on 32 bit,
 379 `elwidth=0b00` specifies that this behaviour is unmodified.  Likewise
 380 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
 381 states that, again, the behaviour is not to be modified.
 382
 383 Only when elwidth is nonzero is the element width overridden to the
 384 explicitly required value.
 385
 386 ## Elwidth for Integers:
 387
 388 | Value | Mnemonic       | Description                        |
 389 |-------|----------------|------------------------------------|
 390 | 00    | DEFAULT        | default behaviour for operation    |
 391 | 01    | `ELWIDTH=b`    | Byte: 8-bit integer                  |
 392 | 10    | `ELWIDTH=h`    | Halfword: 16-bit integer             |
 393 | 11    | `ELWIDTH=w`    | Word: 32-bit integer                 |
 394
 395 ## Elwidth for FP Registers:
 396
 397 | Value | Mnemonic       | Description                        |
 398 |-------|----------------|------------------------------------|
 399 | 00    | DEFAULT        | default behaviour for FP operation     |
 400 | 01    | `ELWIDTH=bf16` | Reserved for `bf16` |
 401 | 10    | `ELWIDTH=f16`  | 16-bit IEEE 754 Half floating-point   |
 402 | 11    | `ELWIDTH=f32`  | 32-bit IEEE 754 Single floating-point  |
 403
 404 Note:
 405 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
 406 is reserved for a future implementation of SV
 407
 408 ## Elwidth for CRs:
 409
 410 TODO, important, particularly for crops, mfcr and mtcr, what elwidth
 411 even means.  instead it may be possible to use the bits as extra indices
 412 (EXTRA6) to access the full 64 CRs.  TBD, several ideas
 413
 414 The actual width of the CRs cannot be altered: they are 4 bit.  Also,
 415 for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
 416 the INT/FP result to which the elwidth override applies, *not* the CR.
 417 This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
 418
 419 As mentioned TBD, this leaves crops etc. to have a meaning defined for
 420 elwidth, because these ops are pure explicit CR based.
 421
 422 Examples: mfxm may take the extra bits and use them as extra mask bits.
 423
 424 # SUBVL Encoding
 425
 426 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
 427 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
 428 lines up in combination with all other "default is all zeros" behaviour.
 429
 430 | Value | Mnemonic  | Subvec  | Description            |
 431 |-------|-----------|---------|------------------------|
 432 | 00    | `SUBVL=1` | single  | Sub-vector length of 1 |
 433 | 01    | `SUBVL=2` | vec2    | Sub-vector length of 2 |
 434 | 10    | `SUBVL=3` | vec3    | Sub-vector length of 3 |
 435 | 11    | `SUBVL=4` | vec4    | Sub-vector length of 4 |
 436
 437 The SUBVL encoding value may be thought of as an inclusive range of a
 438 sub-vector.  SUBVL=2 represents a vec2, its encoding is 0b01, therefore
 439 this may be considered to be elements 0b00 to 0b01 inclusive.
 440
 441 # MASK/MASK_SRC & MASK_KIND Encoding
 442
 443 One bit (`MASKMODE`) indicates the mode: CR or Int predication.   The two
 444 types may not be mixed.
 445
 446 Special note: to get default behaviour (SV disabled) this field must
 447 be set to zero in combination with Integer Predication also being set
 448 to 0b000. this has the effect of enabling "all 1s" in the predicate
 449 mask, which is equivalent to "not having any predication at all"
 450 and consequently, in combination with all other default zeros, fully
 451 disables SV.
 452
 453 | Value | Description                                          |
 454 |-------|------------------------------------------------------|
 455 | 0     | MASK/MASK_SRC are encoded using Integer Predication  |
 456 | 1     | MASK/MASK_SRC are encoded using CR-based Predication |
 457
 458 Integer Twin predication has a second set of 3 bits that uses the same
 459 encoding thus allowing either the same register (r3 or r10) to be used
 460 for both src and dest, or different regs (one for src, one for dest).
 461
 462 Likewise CR based twin predication has a second set of 3 bits, allowing
 463 a different test to be applied.
 464
 465 ## Integer Predication (MASK_KIND=0)
 466
 467 When the predicate mode bit is zero the 3 bits are interpreted as below.
 468 Twin predication has an identical 3 bit field similarly encoded.
 469
 470 | Value | Mnemonic | Element `i` enabled if:      |
 471 |-------|----------|------------------------------|
 472 | 000   | ALWAYS   | predicate effectively all 1s |
 473 | 001   | 1 << R3  | `i == R3`                    |
 474 | 010   | R3       | `R3 & (1 << i)` is non-zero  |
 475 | 011   | ~R3      | `R3 & (1 << i)` is zero      |
 476 | 100   | R10      | `R10 & (1 << i)` is non-zero |
 477 | 101   | ~R10     | `R10 & (1 << i)` is zero     |
 478 | 110   | R30      | `R30 & (1 << i)` is non-zero |
 479 | 111   | ~R30     | `R30 & (1 << i)` is zero     |
 480
 481 ## CR-based Predication (MASK_KIND=1)
 482
 483 When the predicate mode bit is one the 3 bits are interpreted as below.
 484 Twin predication has an identical 3 bit field similarly encoded
 485
 486 | Value | Mnemonic | Element `i` is enabled if     |
 487 |-------|----------|--------------------------|
 488 | 000   | lt       | `CR[offs+i].LT` is set   |
 489 | 001   | nl/ge    | `CR[offs+i].LT` is clear |
 490 | 010   | gt       | `CR[offs+i].GT` is set   |
 491 | 011   | ng/le    | `CR[offs+i].GT` is clear |
 492 | 100   | eq       | `CR[offs+i].EQ` is set   |
 493 | 101   | ne       | `CR[offs+i].EQ` is clear |
 494 | 110   | so/un    | `CR[offs+i].FU` is set   |
 495 | 111   | ns/nu    | `CR[offs+i].FU` is clear |
 496
 497 CR based predication.  TODO: select alternate CR for twin predication? see
 498 [[discussion]]  Overlap of the two CR based predicates must be taken
 499 into account, so the starting point for one of them must be suitably
 500 high, or accept that for twin predication VL must not exceed the range
 501 where overlap will occur, *or* that they use the same starting point
 502 but select different *bits* of the same CRs
 503
 504 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below).  Rc=1 operations start from CR8 (TBD).
 505
 506 # Appendix
 507
 508 Now at its own page: [[svp64/appendix]]
 509