openpower/sv/svp64.mdwn

   1 # SVP64 for OpenPOWER ISA v3.0B
   2
   3 This document describes SV augmentation of the OpenPOWER v3.0B ISA. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the OpenPOWER Foundation (only v3.0B)
   4
   5 Links:
   6
   7 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
   8 * [[svp64/discussion]]
   9 * [[svp64/appendix]]
  10 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
  11 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
  12
  13 Table of contents
  14
  15 [[!toc]]
  16
  17 # Introduction
  18
  19 This document focuses on the encoding of [[SV|sv]], and assimes familiarity with the same. It it best read in conjunction with the [[sv/overview]] which explains the background.
  20
  21 The plan is to create an encoding for SVP64, then to create an encoding
  22 for SVP48, then to reorganize them both to improve field overlap,
  23 reducing the amount of decoder hardware necessary.
  24
  25 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
  26 and counting up as you move to the LSB end). All bit ranges are inclusive
  27 (so `4:6` means bits 4, 5, and 6).
  28
  29 64-bit instructions are split into two 32-bit words, the prefix and the
  30 suffix. The prefix always comes before the suffix in PC order.
  31
  32 | 0:5    | 6:31         | 0:31         |
  33 |--------|--------------|--------------|
  34 | EXT01  | v3.1B Prefix | v3.1B Suffix |
  35
  36 svp64 fits into the "reserved" portions of the v3.1B prefix, making it possible for svp64, v3.0B (or v3.1B including 64 bit prefixed) instructions  to co-exist in the same binary without conflict.
  37
  38 # Definition of Reserved in this spec.
  39
  40 For the new fields added in SVP64, instructions that have any of their
  41 fields set to a reserved value must cause an illegal instruction trap,
  42 to allow emulation of future instruction sets.
  43
  44 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero.
  45
  46 # Identity Behaviour
  47
  48 SVP64 is designed so that when the prefix is all zeros, and
  49  VL=1, no effect or
  50 influence occurs (no augmentation) such that all standard OpenPOWER
  51 v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
  52
  53 Note that this is completely different from when VL=0.  VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
  54  whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction  (an "identity operation").
  55
  56 # Register Naming and size
  57
  58 SV Registers are simply the INT, FP and CR register files extended
  59 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
  60
  61 Where the integer regfile in standard scalar
  62 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
  63 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
  64 extended to 64 entries, CR0 thru CR63.
  65
  66 The names of the registers therefore reflects a simple linear extension
  67 of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this
  68 would be reflected by a linear increase in the size of the underlying
  69 SRAM used for the regfiles.
  70
  71 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
  72 so that the register fields are identical to as if SV was not in effect
  73 i.e. under these circumstances (EXTRA=0) the register field names RA,
  74 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.  This is part of
  75 `scalar identity behaviour` described above.
  76
  77 ## Future expansion.
  78
  79 With the way that EXTRA fields are defined and applied to register fields,
  80 future versions of SV may involve 256 or greater registers.  To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
  81 requiring additional prefix bits.  Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register).  Beyond this, further discussion is out of scope for this version of svp64.
  82
  83 # Remapped Encoding (`RM[0:23]`)
  84
  85 To allow relatively easy remapping of which portions of the Prefix Opcode
  86 Map are used for SVP64 without needing to rewrite a large portion of the
  87 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
  88 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
  89 at the LSB.
  90
  91 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
  92 is defined in the Prefix Fields section.
  93
  94 ## Prefix Opcode Map (64-bit instruction encoding)
  95
  96 In the original table in the v3.1B OpenPOWER ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
  97
  98 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
  99 empty spaces are yet-to-be-allocated Illegal Instructions.
 100
 101 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
 102 |------|--------|--------|--------|--------|--------|--------|--------|--------|
 103 |000---| 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    | 8LS    |
 104 |001---|        |        |        |        |        |        |        |        |
 105 |010---| 8RR    |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 106 |011---|        |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 107 |100---| MLS    | MLS    | MLS    | MLS    | MLS    | MLS    | MLS    | MLS    |
 108 |101---|        |        |        |        |        |        |        |        |
 109 |110---| MRR    |        |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 110 |111---|        | MMIRR  |        |        | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
 111
 112 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
 113
 114 ## Prefix Fields
 115
 116 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Pregix mode), fields within the v3.1B Prefix Opcode Map are set
 117 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
 118 This is achieved by setting bits 7 and 9 to 1:
 119
 120 | Name       | Bits    | Value | Description                    |
 121 |------------|---------|-------|--------------------------------|
 122 | EXT01      | `0:5`   | `1`   | Indicates Prefixed 64-bit      |
 123 | `RM[0]`    | `6`     |       | Bit 0 of Remapped Encoding     |
 124 | SVP64_7    | `7`     | `1`   | Indicates this is SVP64        |
 125 | `RM[1]`    | `8`     |       | Bit 1 of Remapped Encoding     |
 126 | SVP64_9    | `9`     | `1`   | Indicates this is SVP64        |
 127 | `RM[2:23]` | `10:31` |       | Bits 2-23 of Remapped Encoding |
 128
 129 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
 130 are constructed:
 131
 132 | 0:5    | 6     | 7 | 8     | 9 | 10:31    |
 133 |--------|-------|---|-------|---|----------|
 134 | EXT01  | RM    | 1 | RM    | 1 | RM       |
 135 | 000001 | RM[0] | 1 | RM[1] | 1 | RM]2:23] |
 136
 137 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
 138 instruction.  That instruction becomes "prefixed" with the SVP context: the
 139 Remapped Encoding field (RM).
 140
 141 # Remapped Encoding Fields
 142
 143 Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
 144 variants.  There are two categories:  Single and Twin Predication.
 145 Due to space considerations further subdivision of Single Predication
 146 is based on whether the number of src operands is 2 or 3.
 147
 148 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
 149 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
 150 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
 151 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
 152 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
 153
 154 ## Common RM fields
 155
 156 The following fields are common to all Remapped Encodings:
 157
 158
 159 | Field Name | Field bits | Description                            |
 160 |------------|------------|----------------------------------------|
 161 | MASK\_KIND    | `0`        | Execution (predication) Mask Kind                 |
 162 | MASK          | `1:3`      | Execution Mask                      |
 163 | ELWIDTH       | `4:5`      | Element Width                       |
 164 | SUBVL         | `6:7`      | Sub-vector length                   |
 165 | MODE          | `19:23` | changes Vector behaviour               |
 166
 167 Bits 9 to 18 are further decoded depending on RM category for the instruction.
 168
 169 ## RM-1P-3S1D
 170
 171 | Field Name | Field bits | Description                            |
 172 |------------|------------|----------------------------------------|
 173 | Rdest\_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 174 | Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 175 | Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 176 | Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding)   |
 177 | reserved      | `16`    | reserved                               |
 178
 179 ## RM-1P-2S1D
 180
 181 | Field Name | Field bits | Description                               |
 182 |------------|------------|-------------------------------------------|
 183 | Rdest\_EXTRA3 | `8:10`  | extends Rdest  |
 184 | Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1  |
 185 | Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3    |
 186 | ELWIDTH_SRC   | `17:18` | Element Width for Source      |
 187
 188 These are for 2 operand 1 dest instructions, such as `add RT, RA,
 189 RB`. However also included are unusual instructions with an implicit dest
 190 that is identical to its src reg, such as `rlwinmi`.
 191
 192 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
 193 an alternative destination.  With SV however this becomes possible.
 194 Therefore, the fact that the dest is implicitly also a src should not
 195 mislead: due to the *prefix* they are different SV regs.
 196
 197 * `rlwimi RA, RS, ...`
 198 * Rsrc1_EXTRA3 applies to RS as the first src
 199 * Rsrc2_EXTRA3 applies to RA as the secomd src
 200 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
 201
 202 With the addition of the EXTRA bits, the three registers
 203 each may be *independently* made vector or scalar, and be independently
 204 augmented to 7 bits in length.
 205
 206 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 207
 208 ## RM-2P-1S1D/2S
 209
 210 | Field Name | Field bits | Description                 |
 211 |------------|------------|----------------------------|
 212 | Rdest_EXTRA3 | `8:10`     | extends Rdest             |
 213 | Rsrc1_EXTRA3 | `11:13`    | extends Rsrc1             |
 214 | MASK_SRC     | `14:16`    | Execution Mask for Source |
 215 | ELWIDTH_SRC  | `17:18`    | Element Width for Source  |
 216
 217 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 218
 219 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
 220
 221 ## RM-2P-2S1D/1S2D/3S
 222
 223 The primary purpose for this encoding is for Twin Predication on LOAD
 224 and STORE operations.  see [[sv/ldst]] for detailed anslysis.
 225
 226 RM-2P-2S1D:
 227
 228 | Field Name | Field bits | Description                     |
 229 |------------|------------|----------------------------|
 230 | Rdest_EXTRA2 | `8:9`   | extends Rdest (R\*\_EXTRA2 Encoding)   |
 231 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding)   |
 232 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding)   |
 233 | MASK_SRC     | `14:16`    | Execution Mask for Source     |
 234 | ELWIDTH_SRC  | `17:18`    | Element Width for Source      |
 235
 236 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
 237 is in bits 8:9, Rdest1_EXTRA2 in 10:11)
 238
 239 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
 240
 241 Note also that LD with update indexed, which takes 2 src and 2 dest
 242 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
 243 Twin Predication.  therefore these are treated as RM-2P-2S1D and the
 244 src spec for RA is also used for the same RA as a dest.
 245
 246 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
 247
 248 # Mode
 249
 250 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 251
 252 These are the modes:
 253
 254 * **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
 255 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.
 256   *VL is altered as a result*.
 257 * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
 258 * **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see separate section below.
 259   note that there are comprehensive caveats when using this mode.
 260 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  This scheme does not apply to crops (crand, cror).  See appendix for details.
 261
 262 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL.
 263
 264 The Mode table is laid out as follows:
 265
 266 | 0-1 |  2  |  3   4  |  description              |
 267 | --- | --- |---------|-------------------------- |
 268 | 00  |   0 |  sz  dz | normal mode                      |
 269 | 00  |   1 | sz CRM  | reduce mode (mapreduce), SUBVL=1 |
 270 | 00  |   1 | SVM CRM | subvector reduce mode, SUBVL>1   |
 271 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 272 | 01  | inv | sz  RC1 |  Rc=0: ffirst z/nonz |
 273 | 10  |   N | sz   dz |  sat mode: N=0/1 u/s |
 274 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 275 | 11  | inv | sz  RC1 |  Rc=0: pred-result z/nonz |
 276
 277 Fields:
 278
 279 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
 280 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 281 * **CRM** affects the CR on reduce mode when Rc=1
 282 * **SVM** sets "subvector" reduce mode
 283 * **N** sets signed/unsigned saturation.
 284 **RC1** as if Rc=1, stores CRs *but not the result*
 285
 286 # R\*\_EXTRA2 and R\*\_EXTRA3 Encoding
 287
 288 EXTRA is the means by which two things are achieved:
 289
 290 1. Registers are marked as either Vector *or Scalar*
 291 2. Register field numbers (limited typically to 5 bit)
 292    are extended in range, both for Scalar and Vector.
 293
 294 In the following tables register numbers are constructed from the
 295 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
 296 or EXTRA3 field from the SV Prefix.  The prefixing is arranged so that
 297 interoperability between prefixing and nonprefixing of scalar registers
 298 is direct and convenient (when the EXTRA field is all zeros).
 299
 300 A pseudocode algorithm explains the relationship, for INT/FP (see separate section for CRs)
 301
 302     if extra3_mode:
 303         spec = EXTRA3
 304     else:
 305         spec = EXTRA2 << 1 # same as EXTRA3, shifted
 306     if spec[2]: # vector
 307          return (RA << 2) | spec[0:1]
 308     else:         # scalar
 309          return (spec[0:1] << 5) | RA
 310
 311 ## INT/FP EXTRA3
 312
 313 alternative which is understandable and, if EXTRA3 is zero, maps to
 314 "no effect" (scalar OpenPOWER ISA field naming).  also, these are the
 315 encodings used in the original SV Prefix scheme.  the reason why they
 316 were chosen is so that scalar registers in v3.0B and prefixed scalar
 317 registers have access to the same 32 registers.
 318
 319 | R\*\_EXTRA3 | Mode | Range | MSB downto LSB |
 320 |-----------|-------|---------------|---------------------|
 321 | 000       | Scalar | `r0-r31` | `0b00 RA`      |
 322 | 001       | Scalar | `r32-r63` | `0b01 RA`      |
 323 | 010       | Scalar | `r64-r95` | `0b10 RA`      |
 324 | 011       | Scalar | `r96-r127` | `0b11 RA`      |
 325 | 100       | Vector | `r0-r124` | `RA 0b00`      |
 326 | 101       | Vector | `r1-r125` | `RA 0b01`      |
 327 | 110       | Vector | `r2-r126` | `RA 0b10`      |
 328 | 111       | Vector | `r3-r127` | `RA 0b11`      |
 329
 330 ## INT/FP EXTRA2
 331
 332 alternative which is understandable and, if EXTRA2 is zero will map to
 333 "no effect" i.e Scalar OpenPOWER register naming:
 334
 335 | R\*\_EXTRA2 | Mode | Range | MSB down to LSB |
 336 |-----------|-------|---------------|---------------------|
 337 | 00       | Scalar | `r0-r31` | `0b00 RA`                |
 338 | 01       | Scalar | `r32-r63` | `0b01 RA`      |
 339 | 10       | Vector | `r0-r124` | `RA 0b00`      |
 340 | 11       | Vector | `r2-r126` | `RA 0b10`   |
 341
 342 ## CR EXTRA3
 343
 344 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
 345
 346  Encoding shown MSB down to LSB
 347
 348 | R\*\_EXTRA3 | Mode | 7..5    | 4..2    | 1..0    |
 349 |-------------|------|---------| --------|---------|
 350 | 000       | Scalar | 0b000   | BA[4:2] | BA[1:0] |
 351 | 001       | Scalar | 0b001   | BA[4:2] | BA[1:0] |
 352 | 010       | Scalar | 0b010   | BA[4:2] | BA[1:0] |
 353 | 011       | Scalar | 0b011   | BA[4:2] | BA[1:0] |
 354 | 100       | Vector | BA[4:2] | 0b000   | BA[1:0] |
 355 | 101       | Vector | BA[4:2] | 0b010   | BA[1:0] |
 356 | 110       | Vector | BA[4:2] | 0b100   | BA[1:0] |
 357 | 111       | Vector | BA[4:2] | 0b110   | BA[1:0] |
 358
 359 ## CR EXTRA2
 360
 361 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
 362
 363 Encoding shown MSB down to LSB
 364
 365 | R\*\_EXTRA2 | Mode   | 7..5    | 4..2    | 1..0    |
 366 |-------------|--------|---------|---------|---------|
 367 | 00          | Scalar | 0b000   | BA[4:2] | BA[1:0] |
 368 | 01          | Scalar | 0b001   | BA[4:2] | BA[1:0] |
 369 | 10          | Vector | BA[4:2] | 0b000   | BA[1:0] |
 370 | 11          | Vector | BA[4:2] | 0b100   | BA[1:0] |
 371
 372 # ELWIDTH Encoding
 373
 374 Default behaviour is set to 0b00 so that zeros follow the convention of
 375 "npt doing anything".  In this case it means that elwidth overrides
 376 are not applicable.  Thus if a 32 bit instruction operates on 32 bit,
 377 `elwidth=0b00` specifies that this behaviour is unmodified.  Likewise
 378 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
 379 states that, again, the behaviour is not to be modified.
 380
 381 Only when elwidth is nonzero is the element width overridden to the
 382 explicitly required value.
 383
 384 ## Elwidth for Integers:
 385
 386 | Value | Mnemonic       | Description                        |
 387 |-------|----------------|------------------------------------|
 388 | 00    | DEFAULT        | default behaviour for operation    |
 389 | 01    | `ELWIDTH=b`    | Byte: 8-bit integer                  |
 390 | 10    | `ELWIDTH=h`    | Halfword: 16-bit integer             |
 391 | 11    | `ELWIDTH=w`    | Word: 32-bit integer                 |
 392
 393 ## Elwidth for FP Registers:
 394
 395 | Value | Mnemonic       | Description                        |
 396 |-------|----------------|------------------------------------|
 397 | 00    | DEFAULT        | default behaviour for FP operation     |
 398 | 01    | `ELWIDTH=bf16` | Reserved for `bf16` |
 399 | 10    | `ELWIDTH=f16`  | 16-bit IEEE 754 Half floating-point   |
 400 | 11    | `ELWIDTH=f32`  | 32-bit IEEE 754 Single floating-point  |
 401
 402 Note:
 403 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
 404 is reserved for a future implementation of SV
 405
 406 ## Elwidth for CRs:
 407
 408 TODO, important, particularly for crops, mfcr and mtcr, what elwidth
 409 even means.  instead it may be possible to use the bits as extra indices
 410 (EXTRA6) to access the full 64 CRs.  TBD, several ideas
 411
 412 The actual width of the CRs cannot be altered: they are 4 bit.  Also,
 413 for Rc=1 operations that produce a result (in RT or FRT) and corresponding CR, it is
 414 the INT/FP result to which the elwidth override applies, *not* the CR.
 415 This therefore inherently places Rc=1 operations firmly out of scope as far as a "meaning" for elwidth on CRs is concerned.
 416
 417 As mentioned TBD, this leaves crops etc. to have a meaning defined for
 418 elwidth, because these ops are pure explicit CR based.
 419
 420 Examples: mfxm may take the extra bits and use them as extra mask bits.
 421
 422 # SUBVL Encoding
 423
 424 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
 425 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
 426 lines up in combination with all other "default is all zeros" behaviour.
 427
 428 | Value | Mnemonic  | Subvec  | Description            |
 429 |-------|-----------|---------|------------------------|
 430 | 00    | `SUBVL=1` | single  | Sub-vector length of 1 |
 431 | 01    | `SUBVL=2` | vec2    | Sub-vector length of 2 |
 432 | 10    | `SUBVL=3` | vec3    | Sub-vector length of 3 |
 433 | 11    | `SUBVL=4` | vec4    | Sub-vector length of 4 |
 434
 435 The SUBVL encoding value may be thought of as an inclusive range of a
 436 sub-vector.  SUBVL=2 represents a vec2, its encoding is 0b01, therefore
 437 this may be considered to be elements 0b00 to 0b01 inclusive.
 438
 439 # MASK/MASK_SRC & MASK_KIND Encoding
 440
 441 One bit (`MASKMODE`) indicates the mode: CR or Int predication.   The two
 442 types may not be mixed.
 443
 444 Special note: to get default behaviour (SV disabled) this field must
 445 be set to zero in combination with Integer Predication also being set
 446 to 0b000. this has the effect of enabling "all 1s" in the predicate
 447 mask, which is equivalent to "not having any predication at all"
 448 and consequently, in combination with all other default zeros, fully
 449 disables SV.
 450
 451 | Value | Description                                          |
 452 |-------|------------------------------------------------------|
 453 | 0     | MASK/MASK_SRC are encoded using Integer Predication  |
 454 | 1     | MASK/MASK_SRC are encoded using CR-based Predication |
 455
 456 Integer Twin predication has a second set of 3 bits that uses the same
 457 encoding thus allowing either the same register (r3 or r10) to be used
 458 for both src and dest, or different regs (one for src, one for dest).
 459
 460 Likewise CR based twin predication has a second set of 3 bits, allowing
 461 a different test to be applied.
 462
 463 ## Integer Predication (MASK_KIND=0)
 464
 465 When the predicate mode bit is zero the 3 bits are interpreted as below.
 466 Twin predication has an identical 3 bit field similarly encoded.
 467
 468 | Value | Mnemonic | Element `i` enabled if:      |
 469 |-------|----------|------------------------------|
 470 | 000   | ALWAYS   | predicate effectively all 1s |
 471 | 001   | 1 << R3  | `i == R3`                    |
 472 | 010   | R3       | `R3 & (1 << i)` is non-zero  |
 473 | 011   | ~R3      | `R3 & (1 << i)` is zero      |
 474 | 100   | R10      | `R10 & (1 << i)` is non-zero |
 475 | 101   | ~R10     | `R10 & (1 << i)` is zero     |
 476 | 110   | R30      | `R30 & (1 << i)` is non-zero |
 477 | 111   | ~R30     | `R30 & (1 << i)` is zero     |
 478
 479 ## CR-based Predication (MASK_KIND=1)
 480
 481 When the predicate mode bit is one the 3 bits are interpreted as below.
 482 Twin predication has an identical 3 bit field similarly encoded
 483
 484 | Value | Mnemonic | Element `i` is enabled if     |
 485 |-------|----------|--------------------------|
 486 | 000   | lt       | `CR[offs+i].LT` is set   |
 487 | 001   | nl/ge    | `CR[offs+i].LT` is clear |
 488 | 010   | gt       | `CR[offs+i].GT` is set   |
 489 | 011   | ng/le    | `CR[offs+i].GT` is clear |
 490 | 100   | eq       | `CR[offs+i].EQ` is set   |
 491 | 101   | ne       | `CR[offs+i].EQ` is clear |
 492 | 110   | so/un    | `CR[offs+i].FU` is set   |
 493 | 111   | ns/nu    | `CR[offs+i].FU` is clear |
 494
 495 CR based predication.  TODO: select alternate CR for twin predication? see
 496 [[discussion]]  Overlap of the two CR based predicates must be taken
 497 into account, so the starting point for one of them must be suitably
 498 high, or accept that for twin predication VL must not exceed the range
 499 where overlap will occur, *or* that they use the same starting point
 500 but select different *bits* of the same CRs
 501
 502 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below).  Rc=1 operations start from CR8 (TBD).
 503