227abd8ce2abcc64368aca70f1fb25a8c98748c8
[libreriscv.git] / openpower / sv / svp64.mdwn
1 # SVP64 Zero-Overhead Loop Prefix Subsystem
2
3 <!-- hide -->
4 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
5 <!-- show -->
6
7 This document describes [[SV|sv]] augmentation of the [[Power|openpower]] v3.0B [[ISA|openpower/isa/]].
8
9 Credits and acknowledgements:
10
11 * Luke Leighton
12 * Jacob Lifshay
13 * Hendrik Boom
14 * Richard Wilbur
15 * Alexandre Oliva
16 * Cesar Strauss
17 * NLnet Foundation, for funding
18 * OpenPOWER Foundation
19 * Paul Mackerras
20 * Brad Frey
21 * Cathy May
22 * Toshaan Bharvani
23 * IBM for the Power ISA itself
24
25 <!-- hide -->
26 Links:
27
28 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
29 * [[svp64/discussion]]
30 * [[svp64/appendix]]
31 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
34 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
35 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
36 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045> External RFC ls010
37 * [[sv/branches]] chapter
38 * [[sv/ldst]] chapter
39
40 Table of contents
41
42 [[!toc]]
43 <!-- show -->
44
45 ## Introduction
46
47 Simple-V is a type of Vectorization best described as a "Prefix Loop
48 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and
49 to the 8086 `REP`[^bib_rep] Prefix instruction. More advanced features are similar
50 to the Z80 `CPIR`[^bib_cpir] instruction.
51
52 [^bib_ldir]: [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
53 [^bib_cpir]: [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)
54 [^bib_rep]: [8086 REP](https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz)
55
56 Except where explicitly stated all bit numbers remain as in the rest of
57 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
58 the left and counting up as you move rightwards to the LSB end). All bit
59 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
60 **All register numbering and element numbering however is LSB0 ordering**
61 which is a different convention from that used elsewhere in the Power ISA.
62
63 The SVP64 prefix always comes before the suffix in PC order and must be
64 considered an independent "Defined Word-instruction"[^dwi] that augments the behaviour of
65 the following instruction (also a Defined Word-instruction), but does **not** change the actual Decoding
66 of that following instruction just because it is Prefixed. Unlike EXT100-163,
67 where the Suffix is considered an entirely new Opcode Space,
68 SVP64-Prefixed instructions must never be treated or regarded
69 as a different Opcode Space.
70
71 [^dwi]: Defined Word-instruction: Power ISA v3.1 Section 1.6
72
73 Two apparent exceptions to the above hard rule exist: SV
74 Branch-Conditional operations and LD/ST-update "Post-Increment"
75 Mode. Post-Increment was considered sufficiently high priority
76 (significantly reducing hot-loop instruction count) that one bit in
77 the Prefix is reserved for it (*Note the intention to release that bit
78 and move Post-Increment instructions to EXT2xx, as part of [[sv/rfc/ls011]]*).
79 Vectorized Branch-Conditional operations "embed" the original Scalar
80 Branch-Conditional behaviour into a much more advanced variant that is
81 highly suited to High-Performance Computation (HPC), Supercomputing,
82 and parallel GPU Workloads.
83
84 *Architectural Resource Allocation note: at present it is possible to perform
85 partial parallel decode of the SVP64 24-bit Encoding Area at the same time
86 as decoding of the Suffix. Multi-Issue Implementations may even
87 Decode multiple 32-bit words in parallel and follow up with a second
88 cycle of joining Prefix and Suffix "after-the-fact".
89 Mixing and overlaying 64-bit Opcode Encodings into the
90 {SVP64 24-bit Prefix}{Defined Word-instruction} space creates
91 a hard dependency that catastrophically damages Multi-Issue Decoding by
92 greatly complexifying Parallel Instruction-Length Detection.
93 Therefore it has to be prohibited to accept RFCs
94 which fundamentally violate the following hard requirement: **under no circumstances**
95 must the use of SVP64 24-bit Suffixes **also** imply a different Opcode space
96 from **any** non-prefixed Word. Even RESERVED or Illegal Words must be
97 Orthogonal.*
98
99 Subset implementations in hardware are permitted, as long as certain
100 rules are followed, allowing for full soft-emulation including future
101 revisions. Compliancy Subsets exist to ensure minimum levels of binary
102 interoperability expectations within certain environments. Details in
103 the [[svp64/appendix]].
104
105 ## SVP64 encoding features
106
107 A number of features need to be compacted into a very small space of
108 only 24 bits:
109
110 * Independent per-register Scalar/Vector tagging and range extension on
111 every register
112 * Element width overrides on both source and destination
113 * Predication on both source and destination
114 * Two different sources of predication: INT and CR Fields
115 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
116 and fail-first mode.
117
118 Different classes of operations require different formats. The earlier
119 sections cover the common formats and the five separate modes have their own
120 section later:
121
122 * CR operations (crops),
123 * Arithmetic/Logical (termed "normal"),
124 * Load/Store Immediate,
125 * Load/Store Indexed,
126 * Branch-Conditional.
127
128 ## Definition of "PO9-Prefixed"
129
130 Used in the context of "A PO9-Prefixed Word" this is a new area similar to EXT100-163
131 that is shared between SVP64-Single, SVP64, 32 Vectorizable new Opcode areas
132 EXT232-263, and a 32-bit area, EXT900, that is also Vectorizable
133 and SVP64-Single extensible in future. See [[sv/po9_encoding]].
134
135 ## Definition of "SVP64-Prefix"
136
137 A 24-bit RISC-Paradigm Encoding area for Loop-Augmentation of the
138 next
139 "Defined Word-instruction-instruction".
140 Used in the context of "An SVP64-Prefixed Defined Word-instruction", as separate and
141 distinct from the 32-bit PO9-Prefix that *holds* a 24-bit SVP64 Prefix.
142
143 ## Definition of "Vectorizable" and "Unvectorizable"
144
145 "Vectorizable" Defined Word-instructions are Scalar instructions that
146 benefit from SVP64 Loop-Prefixing.
147 Conversely, any operation that inherently makes no sense if repeated in a
148 Vector Loop is termed
149 "Unvectorizable" or "Unvectorized". Examples include `sc` or `sync`
150 which have no registers. `mtmsr` is also classed as Unvectorizable
151 because there is only one `MSR`.
152
153 Unvectorized instructions are required to be detected as such if
154 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
155 Trap raised.
156
157 *Architectural Note: Given that a "pre-classification" Decode Phase is
158 required (identifying whether the Suffix - Defined Word-instruction - is
159 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
160 adding "Unvectorized" to this phase is not unreasonable.*
161
162 Vectorizable Defined Word-instructions are **required** to be Vectorized,
163 or they may not be permitted to be added at all to the Power ISA as Defined
164 Word-instructions.
165
166 *Engineering note: implementations may not choose to add Defined Word-instructions
167 without also adding hardware support for SVP64-Prefixing of the same.*
168
169 *ISA Working Group note: Vectorized PackedSIMD instructions if ever proposed
170 should be considered Unvectorizable and except in extreme mitigating circumstances
171 rejected immediately.*
172
173 ## Definition of Strict Element-Level Execution Order<a name="svp64_eeo"> </a>
174
175 Where Instruction Execution Order[^ieo] guarantees the appearance of sequential
176 execution of instructions, Simple-V requires a corresponding guarantee for Elements
177 because in Simple-V "Execution of Elements" is synonymous with "Execution of
178 instructions".
179
180 [^ieo]: Strict Instruction Execution Order is defined in Public v3.1 Book I Section 2.2
181
182 ## Precise Interrupt Guarantees
183
184 Strict Instruction Execution Order is defined as giving the appearance, as far
185 as programs are concerned, that instructions were executed
186 strictly in the sequence that they occurred. A "Precise"
187 out-of-order
188 Micro-architecture goes to considerable lengths to ensure that
189 this is the case.
190
191 Many Vector ISAs allow interrupts to occur in the middle of
192 processing of large Vector operations, only under the condition
193 that partial results are cleanly discarded, and continuation on return
194 from the Trap Handler will restart the entire operation.
195 The reason is that saving of full Architectural State is
196 not practical. An example would be a Floating-Point Horizontal Sum instruction
197 (very common in Vector ISAs) or a Dot Product instruction
198 that specifies a higher degree of accuracy for the *internal*
199 accumulator than the registers.
200
201 Simple-V operates on an entirely different paradigm from traditional
202 Vector ISAs: as a "Sub-Execution Context", where "Elements" are synonymous
203 with Scalar instructions. With this in mind
204 implementations must observe Strict **Element**-Level Execution Order[[#svp64_eeo]]
205 at all times.
206 *Any* element is Interruptible, and Architectural State may
207 be fully preserved and restored regardless of that same State.
208
209 *Engineering note: implementations are permitted have higher latency to
210 perform context-switching (particularly if REMAP
211 is active).*
212
213 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
214 but the full SVP64 Architectural State may be saved and
215 restored through manual copying of `SVSTATE` (and the four
216 REMAP SPRs if in use at the time, which may be determined by
217 `SVSTATE[32:46]` being non-zero).
218
219 *Programmer's note: Trap Handlers (and any stack-based context save/restore)
220 must avoid the use of SVP64 Prefixed instructions to perform the necessary
221 save/restore of Simple-V Architectural State (SPR SVSTATE),
222 just as use of FPRs and VSRs is presently avoided.
223 However once saved, and set to known-good, SVP64 Prefixed instructions
224 may be used to save/restore GPRs, SPRs, FPRs and other state.*
225
226 *Programmer's note: SVSHAPE0-3 alters Element Execution Order, but only
227 if activated in SVSHAPE. It is therefore technically possible in a Trap
228 Handler to save SVSTATE (`mfspr t0, SVSTATE`), then clear bits 32-46.
229 At this point it becomes safe to use SVP64 to save sequential batches
230 of SPRs (`setvli MAXVL=VL=4; sv.mfspr *t0, *SVSHAPE0`)*
231
232 The only major caveat for REMAP is that
233 after an explicit change to
234 Architectural State caused by writing to the
235 Simple-V SPRs, some implementations may find
236 it easier to take longer to calculate where in a given Schedule
237 the re-mapping Indices were. Obvious examples include Interrupts occuring
238 in the middle of a non-RADIX2 Matrix Multiply Schedule (5x3 by 3x3
239 for example), which
240 will force some implementations to perform divide and modulo
241 calculations.
242
243 An additional caveat involves Condition Register Fields
244 when also used as Predicate Masks. An operation that
245 overwrites the same CR Fields that are simultaneously
246 being used as a Predicate Mask should exercise extreme care
247 if the overwritten CR field element was needed by a
248 subsequent Element for its Predicate Mask bit.
249
250 Some implementations may deploy Cray's technique of
251 "Vector Chaining" (including in this case reading the CR field
252 containing the Predicate bit until the very last moment),
253 and consequently avoiding the risk of
254 overwrite is the responsibility of the Programmer.
255 `hphint` may be used here to good effect.
256 Extra Special care is particularly needed here when using REMAP
257 and also Vertical-First Mode.
258
259 The simplest option is to use Integer Predicate Masks but the
260 caveats are stricter:
261
262 * In Vertical-First loops Programmers **must not** write to any
263 Integers (r3, r0, r31) used as Predicate Masks. Doing so
264 is `UNDEFINED` behaviour.
265 * An **entire** Vector is held up on Horizontal-First Mode if the
266 Integer Predicate is still in in-flight Reservation Stations
267 or pipelines. Speculative Vector Chained Execution mitigates delays
268 but can be heavy on Reservation Station resources.
269
270 ## Register files, elements, and Element-width Overrides
271
272 The relationship between register files, elements, and element-width
273 overrides is expressed as follows:
274
275 * register files are considered to be *byte-level* contiguous SRAMs,
276 accessed exclusively in Little-Endian Byte-Order at all times
277 * elements are sequential contiguous unbounded arrays starting at the "address"
278 of any given 64-bit GPR or FPR, numbered from 0 as the first,
279 "spilling" into numerically-sequentially-increasing GPRs
280 * element-width overrides set the width of the *elements* in the
281 sequentially-numbered contiguous array.
282
283 The relationship is best defined in Canonical form, below, in ANSI c as a
284 union data structure. A key difference is that VSR elements are bounded
285 fixed at 128-bit, where SVP64 elements are conceptually unbounded and
286 only limited by the Maximum Vector Length.
287
288 *Future specification note: SVP64 may be defined on top of VSRs in future.
289 At which point VSX also gains conceptually unbounded VSR register elements*
290
291 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR
292 Register files are expanded from 32 to 128 entries, and the number of
293 CR Fields expanded from CR0-CR7 to CR0-CR127. (Note: A future version
294 of SVP64 is anticipated to extend the VSR register file).
295
296 Memory access remains exactly the same: the effects of `MSR.LE` remain
297 exactly the same, affecting as they already do and remain **only**
298 on the Load and Store memory-register operation byte-order, and having
299 nothing to do with the ordering of the contents of register files or
300 register-register arithmetic or logical operations.
301
302 The only major impact on Arithmetic and Logical operations is that all
303 Scalar operations are defined, where practical and workable, to have
304 three new widths: elwidth=32, elwidth=16, elwidth=8.
305
306 *Architectural note: a future revision of SVP64 for VSX may have entirely
307 different definitions of possible elwidths.*
308
309 The default of
310 elwidth=64 is the pre-existing (Scalar) behaviour which remains 100%
311 unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit
312 variant of `addi`, but the sole exclusive difference is the width.
313 *In no way* is the actual `addi` instruction fundamentally altered
314 to become an entirely different operation (such as a subtract or multiply).
315 FP Operations elwidth overrides are also defined, as explained in
316 the [[svp64/appendix]].
317
318 To be absolutely clear:
319
320 ```
321 There are no conceptual arithmetic ordering or other changes over the
322 Scalar Power ISA definitions to registers or register files or to
323 arithmetic or Logical Operations, beyond element-width subdivision
324 ```
325
326 Element offset
327 numbering is naturally **LSB0-sequentially-incrementing from zero, not
328 MSB0-incrementing** including when element-width overrides are used,
329 at which point the elements progress through each register
330 sequentially from the LSB end
331 (confusingly numbered the highest in MSB0 ordering) and progress
332 incrementally to the MSB end (confusingly numbered the lowest in
333 MSB0 ordering).
334
335 When exclusively using MSB0-numbering, SVP64 becomes unnecessarily complex
336 to both express and subsequently understand: the required conditional
337 subtractions from 63, 31, 15 and 7 needed to express the fact that
338 elements are LSB0-sequential unfortunately become a hostile minefield,
339 obscuring both intent and meaning. Therefore for the purposes of this
340 section the more natural **LSB0 numbering is assumed** and it is left
341 to the reader to translate to MSB0 numbering.
342
343 The Canonical specification for how element-sequential numbering and
344 element-width overrides is defined is expressed in the following c
345 structure, assuming a Little-Endian system, and naturally using LSB0
346 numbering everywhere because the ANSI c specification is inherently LSB0.
347 Note the deliberate similarity to how VSX register elements are defined,
348 from Figure 97, Book I, Section 6.3, Page 258:
349
350 ```
351 #pragma pack
352 typedef union {
353 uint8_t actual_bytes[8];
354 // all of these are very deliberately unbounded arrays
355 // that intentionally "wrap" into subsequent actual_bytes...
356 uint8_t bytes[]; // elwidth 8
357 uint16_t hwords[]; // elwidth 16
358 uint32_t words[]; // elwidth 32
359 uint64_t dwords[]; // elwidth 64
360
361 } el_reg_t;
362
363 // ... here, as packed statically-defined GPRs.
364 elreg_t int_regfile[128];
365
366 // use element 0 as the destination
367 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
368 switch (width) {
369 case 64: el->dwords[0] = int_regfile[gpr].dwords[element];
370 case 32: el->words[0] = int_regfile[gpr].words[element];
371 case 16: el->hwords[0] = int_regfile[gpr].hwords[element];
372 case 8 : el->bytes[0] = int_regfile[gpr].bytes[element];
373 }
374 }
375
376 // use element 0 as the source
377 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
378 switch (width) {
379 case 64: int_regfile[gpr].dwords[element] = el->dwords[0];
380 case 32: int_regfile[gpr].words[element] = el->words[0];
381 case 16: int_regfile[gpr].hwords[element] = el->hwords[0];
382 case 8 : int_regfile[gpr].bytes[element] = el->bytes[0];
383 }
384 }
385 ```
386
387 Example Vector-looped add operation implementation when elwidths are 64-bit:
388
389 ```
390 # vector-add RT, RA,RB using the "uint64_t" union member, "dwords"
391 for i in range(VL):
392 int_regfile[RT].dword[i] = int_regfile[RA].dword[i] + int_regfile[RB].dword[i]
393 ```
394
395 However if elwidth overrides are set to 16 for both source and destination:
396
397 ```
398 # vector-add RT, RA, RB using the "uint64_t" union member "hwords"
399 for i in range(VL):
400 int_regfile[RT].hwords[i] = int_regfile[RA].hwords[i] + int_regfile[RB].hwords[i]
401 ```
402
403 The most fundamental aspect here to understand is that the wrapping
404 into subsequent Scalar GPRs that occurs on larger-numbered elements
405 including and especially on smaller element widths is **deliberate
406 and intentional**. From this Canonical definition it should be clear
407 that sequential elements begin at the LSB end of any given underlying
408 Scalar GPR, progress to the MSB end, and then to the LSB end of the
409 *next numerically-larger Scalar GPR*. In the example above if VL=5
410 and RT=1 then the contents of GPR(1) and GPR(2) will be as follows.
411 For clarity in the table below:
412
413 * Both MSB0-ordered bitnumbering *and* LSB-ordered bitnumbering are shown
414 * The GPR-numbering is considered LSB0-ordered
415 * The Element-numbering (result0-result4) is LSB0-ordered
416 * Each of the results (result0-result4) are 16-bit
417 * "same" indicates "no change as a result of the Vectorized add"
418
419 ```
420 | MSB0: | 0:15 | 16:31 | 32:47 | 48:63 |
421 | LSB0: | 63:48 | 47:32 | 31:16 | 15:0 |
422 |--------|---------|---------|---------|---------|
423 | GPR(0) | same | same | same | same |
424 | GPR(1) | result3 | result2 | result1 | result0 |
425 | GPR(2) | same | same | same | result4 |
426 | GPR(3) | same | same | same | same |
427 | ... | ... | ... | ... | ... |
428 | ... | ... | ... | ... | ... |
429 ```
430
431 Note that the upper 48 bits of GPR(2) would **not** be modified due to
432 the example having VL=5. Thus on "wrapping" - sequential progression
433 from GPR(1) into GPR(2) - the 5th result modifies **only** the bottom
434 16 LSBs of GPR(1).
435
436 If the 16-bit operation were to be followed up with a 32-bit Vectorized
437 Operation, the exact same contents would be viewed as follows:
438
439 ```
440 | MSB0: | 0:31 | 32:63 |
441 | LSB0: | 63:32 | 31:0 |
442 |--------|----------------------|----------------------|
443 | GPR(0) | same | same |
444 | GPR(1) | (result3 || result2) | (result1 || result0) |
445 | GPR(2) | same | (same || result4) |
446 | GPR(3) | same | same |
447 | ... | ... | ... |
448 | ... | ... | ... |
449 ```
450
451 In other words, this perspective really is no different from the situation
452 where the actual Register File is treated as an Industry-standard
453 byte-level-addressable Little-Endian-addressed SRAM. Note that
454 this perspective does **not** involve `MSR.LE` in any way shape or
455 form because `MSR.LE` is directly in control of the Memory-to-Register
456 byte-ordering. This section is exclusively about how to correctly perceive
457 Simple-V-Augmented **Register** Files.
458
459 *Engineering note: to avoid a Read-Modify-Write at the register
460 file it is strongly recommended to implement byte-level write-enable lines
461 exactly as has been implemented in DRAM ICs for many decades. Additionally
462 the predicate mask bit is advised to be associated with the element
463 operation and alongside the result ultimately passed to the register file.
464 When element-width is set to 64-bit the relevant predicate mask bit
465 may be repeated eight times and pull all eight write-port byte-level
466 lines HIGH. Clearly when element-width is set to 8-bit the relevant
467 predicate mask bit corresponds directly with one single byte-level
468 write-enable line. It is up to the Hardware Architect to then amortise
469 (merge) elements together into both PredicatedSIMD Pipelines as well
470 as simultaneous non-overlapping Register File writes, to achieve High
471 Performance designs. Overall it helps to think of the GPR and FPR
472 register files as being much more akin to a 64-bit-wide byte-level-addressable SRAM.*
473
474 **Comparative equivalent using VSR registers**
475
476 For a comparative data point the VSR Registers may be expressed in the
477 same fashion. The c code below is directly an expression of Figure 97 in
478 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating
479 for MSB0 numbering in both bits and elements, adapting in full to LSB0
480 numbering, and obeying LE ordering*.
481
482 **Crucial to understanding why the subtraction from 1,3,7,15 is present is
483 because the Power ISA numbers VSX Registers elements also in MSB0 order**.
484 SVP64 very specifically numbers elements in **LSB0** order with the first
485 element (numbered zero) being at the bitwise-numbered **LSB** end of the
486 register, where VSX does the reverse: places the numerically-*highest*
487 (last-numbered) element at the LSB end of the register.
488
489 ```
490 #pragma pack
491 typedef union {
492 // these do NOT match their Power ISA VSX numbering directly, they are all reversed
493 // bytes[15] is actually VSR.byte[0] for example. if this convention is not
494 // followed then everything ends up in the wrong place
495 uint8_t bytes[16]; // elwidth 8, QTY 16 FIXED total
496 uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total
497 uint32_t words[4]; // elwidth 32, QTY 8 FIXED total
498 uint64_t dwords[2]; // elwidth 64, QTY 2 FIXED total
499 uint8_t actual_bytes[16]; // totals 128-bit
500 } el_reg_t;
501
502 elreg_t VSR_regfile[64];
503
504 static void check_num_elements(int elt, int width) {
505 switch (width) {
506 case 64: assert elt < 2;
507 case 32: assert elt < 4;
508 case 16: assert elt < 8;
509 case 8 : assert elt < 16;
510 }
511 }
512 void get_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
513 check_num_elements(elt, width);
514 switch (width) {
515 case 64: el->dwords[0] = VSR_regfile[gpr].dwords[1-elt];
516 case 32: el->words[0] = VSR_regfile[gpr].words[3-elt];
517 case 16: el->hwords[0] = VSR_regfile[gpr].hwords[7-elt];
518 case 8 : el->bytes[0] = VSR_regfile[gpr].bytes[15-elt];
519 }
520 }
521 void set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
522 check_num_elements(elt, width);
523 switch (width) {
524 case 64: VSR_regfile[gpr].dwords[1-elt] = el->dwords[0];
525 case 32: VSR_regfile[gpr].words[3-elt] = el->words[0];
526 case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[0];
527 case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[0];
528 }
529 }
530 ```
531
532 For VSR Registers one key difference is that the overlay of different
533 element widths is clearly a *bounded static quantity*, whereas for
534 Simple-V the elements are unrestrained and permitted to flow into
535 *successive underlying Scalar registers*. This difference is absolutely
536 critical to a full understanding of the entire Simple-V paradigm and
537 why element-ordering, bit-numbering *and register numbering* are all so
538 strictly defined.
539
540 Implementations are not permitted to violate the Canonical
541 definition. Software will be critically relying on the wrapped (overflow)
542 behaviour inherently implied by the unbounded variable-length c arrays.
543
544 Illustrating the exact same loop with the exact same effect as achieved
545 by Simple-V we are first forced to create wrapper functions, to cater
546 for the fact that VSR register elements are static bounded:
547
548 ```
549 int calc_VSR_reg_offs(int elt, int width) {
550 switch (width) {
551 case 64: return floor(elt / 2);
552 case 32: return floor(elt / 4);
553 case 16: return floor(elt / 8);
554 case 8 : return floor(elt / 16);
555 }
556 }
557 int calc_VSR_elt_offs(int elt, int width) {
558 switch (width) {
559 case 64: return (elt % 2);
560 case 32: return (elt % 4);
561 case 16: return (elt % 8);
562 case 8 : return (elt % 16);
563 }
564 }
565 void _set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
566 int new_elt = calc_VSR_elt_offs(elt, width);
567 int new_reg = calc_VSR_reg_offs(elt, width);
568 set_VSR_element(el, gpr+new_reg, new_elt, width);
569 }
570 ```
571
572 And finally use these functions:
573
574 ```
575 # VSX-add RT, RA, RB using the "uint64_t" union member "hwords"
576 for i in range(VL):
577 el_reg_t result, ra, rb;
578 _get_VSR_element(&ra, RA, i, 16);
579 _get_VSR_element(&rb, RB, i, 16);
580 result.hwords[0] = ra.hwords[0] + rb.hwords[0]; // use array 0 elements
581 _set_VSR_element(&result, RT, i, 16);
582
583 ```
584
585 ## Scalar Identity Behaviour
586
587 SVP64 is designed so that when the prefix is all zeros, and VL=1, no
588 effect or influence occurs (no augmentation) such that all standard Power
589 ISA v3.0/v3.1 instructions covered by the prefix are "unaltered". This
590 is termed `scalar identity behaviour` (based on the mathematical
591 definition for "identity", as in, "identity matrix" or better "identity
592 transformation").
593
594 Note that this is completely different from when VL=0. VL=0 turns all
595 operations under its influence into `nops` (regardless of the prefix)
596 whereas when VL=1 and the SV prefix is all zeros, the operation simply
597 acts as if SV had not been applied at all to the instruction (an
598 "identity transformation").
599
600 The fact that `VL` is dynamic and can be set to any value at runtime
601 based on program conditions and behaviour means very specifically that
602 `scalar identity behaviour` is **not** a redundant encoding. If the only
603 means by which VL could be set was by way of static-compiled immediates
604 then this assertion would be false. VL should not be confused with
605 MAXVL when understanding this key aspect of SimpleV.
606
607 ## Register Naming and size
608
609 As indicated above SV Registers are simply the GPR, FPR and CR register
610 files extended linearly to larger sizes; SV Vectorization iterates
611 sequentially through these registers (LSB0 sequential ordering from 0
612 to VL-1).
613
614 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
615 r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV)
616 as r0 to r127. Likewise FP registers are
617 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
618 CR0 thru CR127. In the Lower SV Compliancy Levels the quantity of registers
619 remains the same in order to reduce implementation cost for Embedded systems.
620
621 The names of the registers therefore reflects a simple linear extension
622 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
623 would be reflected by a linear increase in the size of the underlying
624 SRAM used for the regfiles.
625
626 Note: when an EXTRA field (defined below) is zero, SV is deliberately
627 designed so that the register fields are identical to as if SV was not in
628 effect i.e. under these circumstances (EXTRA=0) the register field names
629 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
630 This is part of `scalar identity behaviour` described above.
631
632 **Condition Register(s)**
633
634 The Scalar Power ISA Condition Register is a 64 bit register where
635 the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used.
636 This convention is *preserved* in SVP64 and an additional 15 Condition
637 Registers provided in order to store the new CR Fields, CR8-CR15,
638 CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition
639 Register are *also* not used: only the bottom 32 bits (numbered 32:63
640 in MSB0 numbering).
641
642 *Programmer's note: using `sv.mfcr` without element-width overrides
643 to take into account the fact that the top 32 MSBs are zero and thus
644 effectively doubling the number of GPR registers required to hold all 128
645 CR Fields would seem the only option because a source elwidth override
646 to 32-bit would take only the bottom 16 LSBs of the Condition Register
647 and set the top 16 LSBs to zeros. However in this case it
648 is possible to use destination element-width overrides (for `sv.mfcr`.
649 source overrides would be used on the GPR of `sv.mtocrf`), whereupon
650 truncation of the 64-bit Condition Register(s) occurs, throwing away
651 the zeros and storing the remaining (valid, desired) 32-bit values
652 sequentially into (LSB0-convention) lower-numbered and upper-numbered
653 halves of GPRs respectively. The programmer is expected to be aware
654 however that the full width of the entire 64-bit Condition Register
655 is considered to be "an element". This is **not** like any other
656 Condition-Register instructions because all other CR instructions,
657 on closer investigation, will be observed to all be CR-bit or CR-Field
658 related. Thus a `VL` of 16 must be used*
659
660 **Condition Register Fields as Predicate Masks**
661
662 Condition Register Fields perform an additional duty in Simple-V: they are
663 used for Predicate Masks. ARM's Scalar Instruction Set calls single-bit
664 predication "Conditional Execution", and utilises Condition Codes for
665 exactly this purpose to solve the problem caused by Branch Speculation.
666 In a Vector ISA context the concept of Predication is naturally extended
667 from single-bit to multi-bit, and the (well-known) benefits become all the
668 more critical given that parallel branches in Vector ISAs are impossible
669 (even a Vector ISA can only have Scalar branches).
670
671 However the Scalar Power ISA does not have Conditional Execution (for
672 which, if it had ever been considered, Condition Register bits would be
673 a perfect natural fit). Thus, when adding Predication using CR Fields
674 via Simple-V it becomes a somewhat disruptive addition to the Power ISA.
675
676 To ameliorate this situation, particularly for pre-existing Hardware
677 designs implementing up to Scalar Power ISA v3.1, some rules are set that
678 allow those pre-existing designs not to require heavy modification to
679 their existing Scalar pipelines. These rules effectively allow Hardware
680 Architects to add the additional CR Fields CR8 to CR127 as if they were
681 an **entirely separate register file**.
682
683 * any instruction involving more than 1 source 1 destination
684 where one of the operands is a Condition Register is prohibited from
685 using registers from both the CR0-7 group and the CR8-127 group at
686 the same time.
687 * any instruction involving 1 source 1 destination where either the
688 source or the destination is a Condition Register is prohibited
689 from setting CR0-7 as a Vector.
690 * prohibitions are required to be enforced by raising Illegal Instruction
691 Traps
692
693 Examples of permitted instructions:
694
695 ```
696 sv.crand *cr8.eq, *cr16.le, *cr40.so # all CR8-CR127
697 sv.mfcr cr5, *cr40 # only one source (CR40) copied to CR5
698 sv.mfcr *cr16, cr40 # Vector-Splat CR40 onto CR16,17,18...
699 sv.mfcr *cr16, cr3 # Vector-Splat CR3 onto CR16,17,18...
700 ```
701
702 Examples of prohibited instructions:
703
704 ```
705 sv.mfcr *cr0, cr40 # Vector-Splat onto CR0,1,2
706 sv.crand cr7, cr9, cr10 # crosses over between CR0-7 and CR8-127
707 ```
708
709 ## Future expansion.
710
711 With the way that EXTRA fields are defined and applied to register
712 fields, future versions of SV may involve 256 or greater registers
713 in some way as long as the reputation of Power ISA for full backwards
714 binary interoperability is preserved. Backwards binary compatibility
715 may be achieved with a PCR bit (Program Compatibility Register) or an
716 MSR bit analogous to SF. Further discussion is out of scope for this
717 version of SVP64.
718
719 Additionally, a future variant of SVP64 will be applied to the Scalar
720 (Quad-precision and 128-bit) VSX instructions. Element-width overrides are
721 an opportunity to expand a future version of the Power ISA to 256-bit,
722 512-bit and 1024-bit operations, as well as doubling or quadrupling the
723 number of VSX registers to 128 or 256. Again further discussion is out
724 of scope for this version of SVP64.
725
726 --------
727
728 \newpage{}
729
730 ## SVP64 Remapped Encoding (`RM[0:23]`)
731
732 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits
733 32-37 are the Primary Opcode of the Suffix "Defined Word-instruction". 38-63 are the
734 remainder of the Defined Word-instruction. Note that the new EXT232-263 SVP64 area
735 it is obviously mandatory that bit 32 is required to be set to 1.
736
737 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
738 |-----|---|---|----------|--------|----------|-----------------------|
739 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
740 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
741
742 It is important to note that unlike EXT1xx 64-bit prefixed instructions
743 there is insufficient space in `RM` to provide identification of
744 any SVP64 Fields without first partially decoding the 32-bit suffix.
745 Similar to the "Forms" (X-Form, D-Form) the `RM` format is individually
746 associated with every instruction. However this still does not adversely
747 affect Multi-Issue Decoding because the identification of the *length*
748 of anything in the 64-bit space has been kept brutally simple (EXT009),
749 and further decoding of any number of 64-bit Encodings in parallel at
750 that point is fully independent.
751
752 Extreme caution and care must be taken when extending SVP64
753 in future, to not create unnecessary relationships between prefix and
754 suffix that could complicate decoding, adding latency.
755
756 ## Common RM fields
757
758 The following fields are common to all Remapped Encodings:
759
760 | Field Name | Field bits | Description |
761 |------------|------------|----------------------------------------|
762 | MASKMODE | `0` | Execution (predication) Mask Kind |
763 | MASK | `1:3` | Execution Mask |
764 | SUBVL | `8:9` | Sub-vector length |
765
766 The following fields are optional or encoded differently depending
767 on context after decoding of the Scalar suffix:
768
769 | Field Name | Field bits | Description |
770 |------------|------------|----------------------------------------|
771 | ELWIDTH | `4:5` | Element Width |
772 | ELWIDTH_SRC | `6:7` | Element Width for Source (or MASK_SRC in 2PM) |
773 | EXTRA | `10:18` | Register Extra encoding |
774 | MODE | `19:23` | changes Vector behaviour |
775
776 * MODE changes the behaviour of the SV operation (result saturation,
777 mapreduce)
778 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
779 and Audio/Video DSP work
780 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
781 source operand width
782 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
783 sources: scalar INT and Vector CR).
784 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
785 for the instruction, which is determined only by decoding the Scalar 32
786 bit suffix.
787
788 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
789 such as `RM-1P-3S1D` which indicates for this example that the operation
790 is to be single-predicated and that there are 3 source operand EXTRA
791 tags and one destination operand tag.
792
793 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
794 or increased latency in some implementations due to lane-crossing.
795
796 ## Mode
797
798 Mode is an augmentation of SV behaviour. Different types of instructions
799 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
800 formats apply to different instruction types. Modes include Reduction,
801 Iteration, arithmetic saturation, and Fail-First. More specific details
802 in each section and in the [[svp64/appendix]]
803
804 * For condition register operations see [[sv/cr_ops]]
805 * For LD/ST Modes, see [[sv/ldst]].
806 * For Branch modes, see [[sv/branches]]
807 * For arithmetic and logical, see [[sv/normal]]
808
809 ## ELWIDTH Encoding
810
811 Default behaviour is set to 0b00 so that zeros follow the convention
812 of `scalar identity behaviour`. In this case it means that elwidth
813 overrides are not applicable. Thus if a 32 bit instruction operates
814 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
815 Likewise when a processor is switched from 64 bit to 32 bit mode,
816 `elwidth=0b00` states that, again, the behaviour is not to be modified.
817
818 Only when elwidth is nonzero is the element width overridden to the
819 explicitly required value.
820
821 ### Elwidth for Integers:
822
823 | Value | Mnemonic | Description |
824 |-------|----------------|------------------------------------|
825 | 00 | DEFAULT | default behaviour for operation |
826 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
827 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
828 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
829
830 This encoding is chosen such that the byte width may be computed as
831 `8<<(3-ew)`
832
833 ### Elwidth for FP Registers:
834
835 | Value | Mnemonic | Description |
836 |-------|----------------|------------------------------------|
837 | 00 | DEFAULT | default behaviour for FP operation |
838 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
839 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
840 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
841
842 Note:
843 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
844 is reserved for a future implementation of SV
845
846 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`)
847 shall perform its operation at **half** the ELWIDTH then padded back out
848 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation
849 that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
850 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
851 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
852 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16 or
853 ELWIDTH=bf16 is reserved and must raise an illegal instruction (IEEE754
854 FP8 or BF8 are not defined).
855
856 ### Elwidth for CRs (no meaning)
857
858 Element-width overrides for CR Fields has no meaning. The bits
859 are therefore used for other purposes, or when Rc=1, the Elwidth
860 applies to the result being tested (a GPR or FPR), but not to the
861 Vector of CR Fields.
862
863 ## SUBVL Encoding
864
865 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
866 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
867 lines up in combination with all other "default is all zeros" behaviour.
868
869 | Value | Mnemonic | Subvec | Description |
870 |-------|-----------|---------|------------------------|
871 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
872 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
873 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
874 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
875
876 The SUBVL encoding value may be thought of as an inclusive range of a
877 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
878 this may be considered to be elements 0b00 to 0b01 inclusive.
879
880 Effectively, SUBVL is like a SIMD multiplier: instead of just 1
881 element operation issued, SUBVL element operations are issued (as an inner loop).
882 The key difference between VL looping and SUBVL looping
883 is that predication bits are applied per
884 **group**, rather than by individual element.
885
886 Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
887
888 ## MASK/MASK_SRC & MASKMODE Encoding
889
890 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
891 types may not be mixed.
892
893 Special note: to disable predication this field must be set to zero in
894 combination with Integer Predication also being set to 0b000. this has the
895 effect of enabling "all 1s" in the predicate mask, which is equivalent to
896 "not having any predication at all".
897
898 `MASKMODE` may be set to one of 2 values:
899
900 | Value | Description |
901 |-----------|------------------------------------------------------|
902 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
903 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
904
905 Integer Twin predication has a second set of 3 bits that uses the same
906 encoding thus allowing either the same register (r3, r10 or r31) to be
907 used for both src and dest, or different regs (one for src, one for dest).
908
909 Likewise CR based twin predication has a second set of 3 bits, allowing
910 a different test to be applied.
911
912 Note that it cannot necessarily be assumed that Predicate Masks
913 (whether INT or CR) are read in full *before* the operations proceed. In practice (for CR Fields)
914 this creates an unnecessary block on parallelism, prohibiting
915 "Vector Chaining". Therefore, it is up
916 to the programmer to ensure that the CR field Elements used as Predicate Masks
917 are not overwritten by any parallel Vector Loop. Doing so results
918 in **UNDEFINED** behaviour, according to the definition outlined in the
919 Power ISA v3.0B Specification.
920
921 Hardware Implementations are therefore free and clear to delay reading
922 of individual CR fields until the actual predicated element operation
923 needs to take place, safe in the knowledge that no programmer will have
924 issued a Vector Instruction where previous elements could have overwritten
925 (destroyed) not-yet-executed CR-Predicated element operations.
926 This particularly is an issue when using REMAP, as the order in
927 which CR-Field-based Predicate Mask bits could be read on a per-element
928 execution basis could well conflict with the order in which prior
929 elements wrote to the very same CR Field.
930
931 Additionally Programmers should avoid using r3 r10 or r30
932 as destination registers when these are also used as a Predicate
933 Mask. Doing so is again UNDEFINED behaviour.
934
935 Usually in 2P `MASK_SRC` is exclusively in the EXTRA area. However for
936 LD/ST-Indexed a different Encoding is required, designated `2PM`.
937
938 ### Integer Predication (MASKMODE=0)
939
940 When the predicate mode bit is zero the 3 bits are interpreted as below.
941 Twin predication has an identical 3 bit field similarly encoded.
942
943 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
944 following meaning:
945
946 | Value | Mnemonic | Element `i` enabled if: |
947 |-------|----------|------------------------------|
948 | 000 | ALWAYS | predicate effectively all 1s |
949 | 001 | 1 << R3 | `i == R3` |
950 | 010 | R3 | `R3 & (1 << i)` is non-zero |
951 | 011 | ~R3 | `R3 & (1 << i)` is zero |
952 | 100 | R10 | `R10 & (1 << i)` is non-zero |
953 | 101 | ~R10 | `R10 & (1 << i)` is zero |
954 | 110 | R30 | `R30 & (1 << i)` is non-zero |
955 | 111 | ~R30 | `R30 & (1 << i)` is zero |
956
957 r10 and r30 are at the high end of temporary and unused registers,
958 so as not to interfere with register allocation from ABIs.
959
960 ### CR-based Predication (MASKMODE=1)
961
962 When the predicate mode bit is one the 3 bits are interpreted as below.
963 Twin predication has an identical 3 bit field similarly encoded.
964
965 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
966 following meaning:
967
968 | Value | Mnemonic | Element `i` is enabled if |
969 |-------|----------|--------------------------|
970 | 000 | lt | `CR[offs+i].LT` is set |
971 | 001 | nl/ge | `CR[offs+i].LT` is clear |
972 | 010 | gt | `CR[offs+i].GT` is set |
973 | 011 | ng/le | `CR[offs+i].GT` is clear |
974 | 100 | eq | `CR[offs+i].EQ` is set |
975 | 101 | ne | `CR[offs+i].EQ` is clear |
976 | 110 | so/un | `CR[offs+i].FU` is set |
977 | 111 | ns/nu | `CR[offs+i].FU` is clear |
978
979 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorized
980 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
981
982 The CR Predicates chosen must start on a boundary that Vectorized CR
983 operations can access cleanly, in full. With EXTRA2 restricting starting
984 points to multiples of 8 (CR0, CR8, CR16...) both Vectorized Rc=1 and
985 CR Predicate Masks have to be adapted to fit on these boundaries as well.
986
987 ## Extra Remapped Encoding <a name="extra_remap"> </a>
988
989 Shows all instruction-specific fields in the Remapped Encoding
990 `RM[10:18]` for all instruction variants. Note that due to the very
991 tight space, the encoding mode is *not* included in the prefix itself.
992 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
993 on a per-instruction basis, and, like "Forms" are given a designation
994 (below) of the form `RM-nP-nSnD`. The full list of which instructions
995 use which remaps is here [[opcode_regs_deduped]].
996
997 **Please note the following**:
998
999 ```
1000 Machine-readable CSV files have been autogenerated which will make the
1001 task of creating SV-aware ISA decoders, documentation, assembler tools
1002 compiler tools Simulators documentation all aspects of SVP64 easier
1003 and less prone to mistakes. Please avoid manual re-creation of
1004 information from the written specification wording in this chapter,
1005 and use the CSV files or use the Canonical tool which creates the CSV
1006 files, named sv_analysis.py. The information contained within
1007 sv_analysis.py is considered to be part of this Specification, even
1008 encoded as it is in python3.
1009 ```
1010
1011
1012 The mappings are part of the SVP64 Specification in exactly the same
1013 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
1014 will need a corresponding SVP64 Mapping, which can be derived by-rote
1015 from examining the Register "Profile" of the instruction.
1016
1017 There are two categories: Single and Twin Predication. Due to space
1018 considerations further subdivision of Single Predication is based on
1019 whether the number of src operands is 2 or 3. With only 9 bits available
1020 some compromises have to be made.
1021
1022 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
1023 instructions (fmadd, isel, madd).
1024 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
1025 instructions (src1 src2 dest)
1026 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
1027 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
1028 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
1029 * `RM-2PM-2S1D` Twin Predication (src=2, dest=1) for LD/ST Update (Indexed)
1030
1031 The `2PM` designation uses bits 6 and 7 as well as the 9 EXTRA bits
1032 in order to extend two registers to
1033 EXTRA3, sacrificing destination elwidths in the process.
1034 `MASK_SRC` has a different encoding in `2PM`.
1035
1036 ### RM-1P-3S1D
1037
1038 | Field Name | Field bits | Description |
1039 |------------|------------|----------------------------------------|
1040 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1041 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1042 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1043 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1044 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
1045
1046 These are for 3 operand in and either 1 or 2 out instructions.
1047 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
1048 such as `maddedu` have an implicit second destination, RS, the
1049 selection of which is determined by bit 18.
1050
1051 ### RM-1P-2S1D
1052
1053 | Field Name | Field bits | Description |
1054 |------------|------------|-------------------------------------------|
1055 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
1056 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
1057 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
1058
1059 These are for 2 operand 1 dest instructions, such as `add RT, RA,
1060 RB`. However also included are unusual instructions with an implicit
1061 dest that is identical to its src reg, such as `rlwinmi`.
1062
1063 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
1064 not have sufficient bit fields to allow an alternative destination.
1065 With SV however this becomes possible. Therefore, the fact that the
1066 dest is implicitly also a src should not mislead: due to the *prefix*
1067 they are different SV regs.
1068
1069 * `rlwimi RA, RS, ...`
1070 * Rsrc1_EXTRA3 applies to RS as the first src
1071 * Rsrc2_EXTRA3 applies to RA as the second src
1072 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
1073
1074 With the addition of the EXTRA bits, the three registers
1075 each may be *independently* made vector or scalar, and be independently
1076 augmented to 7 bits in length.
1077
1078 ### RM-2P-1S1D/2S
1079
1080 | Field Name | Field bits | Description |
1081 |------------|------------|----------------------------|
1082 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1083 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1084 | MASK_SRC | `16:18` | Execution Mask for Source |
1085
1086 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
1087
1088 | Field Name | Field bits | Description |
1089 |------------|------------|----------------------------|
1090 | Rsrc1_EXTRA3 | `10:12` | extends Rsrc1 |
1091 | Rsrc2_EXTRA3 | `13:15` | extends Rsrc2 |
1092 | MASK_SRC | `16:18` | Execution Mask for Source |
1093
1094 ### RM-1P-2S1D
1095
1096 single-predicate, three registers (2 read, 1 write)
1097
1098 | Field Name | Field bits | Description |
1099 |------------|------------|----------------------------|
1100 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1101 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1102 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
1103
1104 ### RM-2P-2S1D/1S2D/3S
1105
1106 The primary purpose for this encoding is for Twin Predication on LOAD
1107 and STORE operations. see [[sv/ldst]] for detailed analysis.
1108
1109 **RM-2P-2S1D:**
1110
1111 | Field Name | Field bits | Description |
1112 |------------|------------|----------------------------|
1113 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1114 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1115 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1116 | MASK_SRC | `16:18` | Execution Mask for Source |
1117
1118 **RM-2P-1S2D:**
1119
1120 For RM-2P-1S2D dest2 is in bits 14:15
1121
1122 | Field Name | Field bits | Description |
1123 |------------|------------|----------------------------|
1124 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1125 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1126 | Rdest2_EXTRA2 | `14:15` | extends Rdest22 (R\*\_EXTRA2 Encoding) |
1127 | MASK_SRC | `16:18` | Execution Mask for Source |
1128
1129 **RM-2P-3S:**
1130
1131 Also that for RM-2P-3S (to cover `stdx` etc.) the names are switched to 3 src:
1132 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
1133
1134 | Field Name | Field bits | Description |
1135 |------------|------------|----------------------------|
1136 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1137 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1138 | Rsrc3_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1139 | MASK_SRC | `16:18` | Execution Mask for Source |
1140
1141 Note also that LD with update indexed, which takes 2 src and
1142 creates 2 dest registers (e.g. `lhaux RT,RA,RB`), does not have room
1143 for 4 registers and also Twin Predication. Therefore these are treated as
1144 RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest.
1145
1146 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
1147 or increased latency in some implementations due to lane-crossing.
1148
1149 ### RM-2PM-2S1D/1S2D/3S
1150
1151 The primary purpose for this encoding is for Twin Predication on LOAD
1152 and STORE operations providing EXTRA3 for RT, RA and RS.
1153 see [[sv/ldst]] for detailed analysis.
1154
1155 **RM-2PM-2S1D:**
1156
1157 RT or RS requires EXTRA3, RA requires EXTRA3, but for RB EXTRA2 will
1158 suffice. `MASK_SRC` may be read from the bits normally used for dest-elwidth.
1159
1160 | Field Name | Field bits | Description |
1161 |------------|------------|----------------------------|
1162 | Rdest_EXTRA3 | `10:12` | extends Rdest (R\*\_EXTRA2 Encoding) |
1163 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1164 | Rsrc2_EXTRA2 | `16:17` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1165 | MASK_SRC | `6:7,18` | Execution Mask for Source |
1166
1167 ## R\*\_EXTRA2/3
1168
1169 EXTRA is the means by which two things are achieved:
1170
1171 1. Registers are marked as either Vector *or Scalar*
1172 2. Register field numbers (limited typically to 5 bit)
1173 are extended in range, both for Scalar and Vector.
1174
1175 The register files are therefore extended:
1176
1177 * INT (GPR) is extended from r0-31 to r0-127
1178 * FP (FPR) is extended from fp0-32 to fp0-fp127
1179 * CR Fields are extended from CR0-7 to CR0-127
1180
1181 However due to pressure in `RM.EXTRA` not all these registers
1182 are accessible by all instructions, particularly those with
1183 a large number of operands (`madd`, `isel`).
1184
1185 In the following tables register numbers are constructed from the
1186 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
1187 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
1188 designation for a given instruction. The prefixing is arranged so that
1189 interoperability between prefixing and nonprefixing of scalar registers
1190 is direct and convenient (when the EXTRA field is all zeros).
1191
1192 A pseudocode algorithm explains the relationship, for INT/FP (see
1193 [[svp64/appendix]] for CRs)
1194
1195 ```
1196 if extra3_mode:
1197 spec = EXTRA3
1198 elif EXTRA2[0]: # vector mode, can express even registers in r0-126
1199 spec = EXTRA2 << 1 # same as EXTRA3, shifted
1200 else: # scalar mode, can express registers in r0-63
1201 spec = (EXTRA2[0] << 2) | EXTRA2[1]
1202 if spec[0]: # vector
1203 return (RA << 2) | spec[1:2]
1204 else: # scalar
1205 return (spec[1:2] << 5) | RA
1206 ```
1207
1208 Future versions may extend to 256 by shifting Vector numbering up.
1209 Scalar will not be altered.
1210
1211 Note that in some cases the range of starting points for Vectors
1212 is limited.
1213
1214 ### INT/FP EXTRA3
1215
1216 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
1217 naming).
1218
1219 Fields are as follows:
1220
1221 * Value: R_EXTRA3
1222 * Mode: register is tagged as scalar or vector
1223 * Range/Inc: the range of registers accessible from this EXTRA
1224 encoding, and the "increment" (accessibility). "/4" means
1225 that this EXTRA encoding may only give access (starting point)
1226 every 4th register.
1227 * MSB..LSB: the bit field showing how the register opcode field
1228 combines with EXTRA to give (extend) the register number (GPR)
1229
1230 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1231
1232 | Value | Mode | Range/Inc | 6..0 |
1233 |-----------|-------|---------------|---------------------|
1234 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
1235 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
1236 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
1237 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
1238 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
1239 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
1240 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
1241 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
1242
1243 ### INT/FP EXTRA2
1244
1245 If EXTRA2 is zero will map to "scalar identity behaviour" i.e Scalar
1246 Power ISA register naming:
1247
1248 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1249
1250 | Value | Mode | Range/inc | 6..0 |
1251 |----------|-------|---------------|-----------|
1252 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
1253 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
1254 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
1255 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
1256
1257 **Note that unlike in EXTRA3, in EXTRA2**:
1258
1259 * the GPR Vectors may only start from
1260 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
1261 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
1262
1263 as there is insufficient bits to cover the full range.
1264
1265 ### CR Field EXTRA3
1266
1267 CR Field encoding is essentially the same but made more complex due to CRs
1268 being bit-based, because the application of SVP64 element-numbering applies
1269 to the CR *Field* numbering not the CR register *bit* numbering.
1270 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
1271 and Scalars may only go from `CR0, CR1, ... CR31`
1272
1273 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1274 BA ranges are in MSB0.
1275
1276 For a 5-bit operand (BA, BB, BT):
1277
1278 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1279 |-------|------|---------------|-----------| --------|---------|
1280 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1281 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1282 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
1283 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
1284 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1285 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
1286 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1287 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
1288
1289 For a 3-bit operand (e.g. BFA):
1290
1291 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1292 |-------|------|---------------|-----------| --------|
1293 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1294 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1295 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
1296 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
1297 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1298 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
1299 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1300 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
1301
1302 ### CR EXTRA2
1303
1304 CR encoding is essentially the same but made more complex due to CRs
1305 being bit-based, because the application of SVP64 element-numbering applies
1306 to the CR *Field* numbering not the CR register *bit* numbering.
1307 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
1308
1309 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1310 BA ranges are in MSB0.
1311
1312 For a 5-bit operand (BA, BB, BC):
1313
1314 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1315 |-------|--------|----------------|---------|---------|---------|
1316 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1317 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1318 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1319 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1320
1321 For a 3-bit operand (e.g. BFA):
1322
1323 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1324 |-------|------|---------------|-----------| --------|
1325 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1326 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1327 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1328 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1329
1330 <!-- hide -->
1331 ## Appendix
1332
1333 Now at its own page: [[svp64/appendix]]
1334
1335
1336 [[!tag standards]]
1337
1338 <!-- show -->
1339
1340 --------
1341
1342 \newpage{}