openpower/sv/svp_rewrite/svp64/discussion.mdwn

   1 # Links
   2
   3 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
   4
   5 # Notes on requirements for bit allocations
   6
   7 do not try to jam VL or MAXVL in.  go with the flow of 24 bits spare.
   8
   9 * 2: SUBVL
  10 * 2: elwidth
  11 * 2: twin-predication (src, dest) elwidth
  12 * 1: select INT or CR predication
  13 * 3: predicate selection and inversion (QTY 2 for tpred)
  14 * 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
  15 * 3: saturate mode
  16
  17 totals: 22 bits (dest elwidth shared)
  18
  19 http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
  20
  21 ## twin predication
  22
  23 twin predication and twin elwidth overrides is extremely important to have to be able to override both the src and dest elwidth yet keep the underlying scalar operation intact.  examples include mr with an elwidth=8, VL=8 on the src will take a byte at a time from one 64 bit reg and place it into 8x 64-bit regs, zero-extended.  more complex operations involve SUBVL and Audio/Video DSP operations, see [[av_opcodes]]
  24
  25 something like:
  26
  27 | 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 12 | 13 18 | 19  20 |
  28 | ----- | --- | --- | ---- | ---- | ----- | ----- | ------ |
  29 | subvl | sew | dew | ptyp | psrc | pdst  | vspec | zmode  |
  30
  31 * subvl - 1 to 4 scalar / vec2 / vec3 / vec4
  32 * sew / dew - DEFAULT / 8 / 16 /32 element width
  33 * ptyp - predication INT / CR
  34 * psrc / pdst - predicate mask selector and inversion
  35 * vspec - 3 bit src / dest scalar-vector extension
  36 * zmode: 2 bit src pred zero mode, dest pred zero mode
  37 * ffirst: 3 bit.  EN and CR index bit.
  38
  39 ## twin predication, CR based.
  40
  41 separate src and dest predicates are a critical part of SV for provision of VEXPAND, VREDUCE, VSPLAT, VINSERT and many more operations.
  42
  43 Twin CR predication could be done in two ways:
  44
  45 * start from different CRs for the src and dest
  46 * start from the same CR.
  47
  48 With different bits being selectable (CR[0..3]) starting from the same CR makes some sense.
  49
  50
  51 # standard arith ops (single predication)
  52
  53 these are of the form res = op(src1, src2, ...)
  54
  55 | 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 18 | 19  23 |
  56 | ----- | --- | --- | ---- | ---- | ----- | ------ |
  57 | subvl | sew | dew | ptyp | pred | vspec | mode   |
  58
  59 * subvl - 1 to 4 scalar / vec2 / vec3 / vec4
  60 * sew / dew - DEFAULT / 8 / 16 /32 element width
  61 * ptyp - predication INT / CR
  62 * pred - predicate mask selector and inversion
  63 * vspec - 2/3 bit src / dest scalar-vector extension
  64 * mode - 5 bit
  65
  66 Mode
  67
  68      0   1   2   3    4    description
  69      ------------------
  70      0   0   0   0    0    nothing
  71      0   1   N        zero sat mode: N=0/1 u/s
  72      1   0   inv CR bit    Rc=1: ffirst CR sel
  73      1   0            zero Rc=0: pred zero mode
  74
  75
  76 For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits.  for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg: total 8 bits.
  77
  78 Note:
  79
  80 * the operation should always be done at max(srcwidth, dstwidth), unless it can
  81   be proven using the lower will lead to the same result
  82 * saturation is done on the result at the **dest** elwidth
  83
  84 Some examples on different operation widths:
  85
  86     u16 / u16 = u8
  87     256 / 2 = 128 # if we used the smaller width, we'd get 0. Wrong
  88
  89     u8 * u8 = u16
  90     255 * 2 = 510 # if we used the smaller width, we'd get 254. Wrong
  91
  92     u16 + u16 = u8
  93     256 + 2 = 2 # this is correct whether we use the larger or smaller width - hw can optimize addition
  94
  95 # Notes about rounding, clamp and saturate
  96
  97 One of the issues with vector ops is that in integer DSP ops for example in Audio the operation must clamp or saturate rather than overflow or ignore the upper bits and become a modulo operation.  This for Audio is extremely important, also to provide an indicator as to whether saturation occurred.  see  [[av_opcodes]].
  98
  99 If there are spare bits it would be very good to look at using some of them to specify the mode, because otherwise a SPR has to be used which will need to be set and unset.  This can get costly.
 100
 101 # Notes about Swizzle
 102
 103 Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.
 104
 105 therefore the strategy proposed is:
 106
 107 * design 16bit scalar ops
 108 * use the 11 bit old SV prefix to create 32bit insns
 109 * when those are embedded into v3.1B 64 prefix, the 24 bits are entirely allocated to swizzle.
 110
 111 with 2x12 this would mean no need to have complex encoding of swizzle.
 112
 113 if we really do need 2 bits spare then the complex encoder of swizzle could be deployed.
 114
 115 # note about INT predicate
 116
 117 001     ALWAYS (implicit)       Operation is not masked
 118
 119 this means by default that 001 will always be in nonpredicated ops, which seems anomalous.  would 000 be better to indicate "no predication"?
 120
 121 000 would indicate "the predicate is an immediate of all 1s" i.e. "no operation is masked out"