openpower/sv/svp_rewrite/svp64/discussion.mdwn

   1 # Notes on requirements for bit allocations
   2
   3 * 2: SUBVL
   4 * 2: elwidth
   5 * 2: twin-predication (src, dest) elwidth
   6 * 1: select INT or CR predication
   7 * 3: predicate selection and inversion (QTY 2 for tpred)
   8 * 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
   9
  10 totals: 22 bits leaving 2 spare for further modes.
  11
  12 http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
  13
  14 ## twin predication
  15
  16 | 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 12 | 13 18 |
  17 | subvl | sew | dew | ptyp | psrc | pdst  | vspec |
  18
  19 # Notes about Swizzle
  20
  21 Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.
  22
  23 therefore the strategy proposed is:
  24
  25 * design 16bit scalar ops
  26 * use the 11 bit old SV prefix to create 32bit insns
  27 * when those are embedded into v3.1B 64 prefix, the 24 bits are entirely allocated to swizzle.
  28
  29 with 2x12 this would mean no need to have complex encoding of swizzle.
  30
  31 if we really do need 2 bits spare then the complex encoder of swizzle could be deployed.
  32