openpower/sv/svp_rewrite/svp64.mdwn

   1 # Rewrite of SVP64 for OpenPower ISA v3.1
   2
   3 [[svp64/discussion]]
   4
   5 The plan is to create an encoding for SVP64, then to create an encoding for
   6 SVP48, then to reorganize them both to improve field overlap, reducing the
   7 amount of decoder hardware necessary.
   8
   9 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB and
  10 counting up as you move to the LSB end). All bit ranges are inclusive (so
  11 `4:6` means bits 4, 5, and 6).
  12
  13 64-bit instructions are split into two 32-bit words, the prefix and the suffix. The prefix always comes before the suffix in PC order.
  14
  15 ## Prefix Opcode Map (64-bit instruction encoding) (prefix bits 6:11)
  16
  17 (shows both PowerISA v3.1 instructions as well as new SVP instructions; empty spaces are yet-to-be-allocated Illegal Instructions)
  18
  19 | bits 6:11 | ---000   | ---001     | ---010   | ---011   | ---100   | ---101   | ---110   | ---111   |
  20 |-----------|----------|------------|----------|----------|----------|----------|----------|----------|
  21 | 000---    | 8LS-form | 8LS-form   | 8LS-form | 8LS-form | 8LS-form | 8LS-form | 8LS-form | 8LS-form |
  22 | 001---    |          |            |          |          |          |          |          |          |
  23 | 010---    | 8RR-form |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  24 | 011---    |          |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  25 | 100---    | MLS-form | MLS-form   | MLS-form | MLS-form | MLS-form | MLS-form | MLS-form | MLS-form |
  26 | 101---    |          |            |          |          |          |          |          |          |
  27 | 110---    | MRR-form |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  28 | 111---    |          | MMIRR-form |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  29
  30 ## Prefix Fields
  31
  32 | Prefix Field Name   | Field bits | Constant Value | Description                            |
  33 |---------------------|------------|----------------|----------------------------------------|
  34 | PO (Primary Opcode) | `0:5`      | `1`            | Indicates this is a 64-bit instruction |
  35 | TBD                 | `6`        |                |                                        |
  36 | SVP64_7             | `7`        | `1`            | Indicates this is a SVP64 instruction  |
  37 | TBD                 | `8`        |                |                                        |
  38 | SVP64_9             | `9`        | `1`            | Indicates this is a SVP64 instruction  |
  39 | TBD                 | `10:31`    |                |                                        |
  40
  41 # Register Naming
  42
  43 SV Registers are numbered using the notation `SV[F]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.
  44
  45 ## Integer Registers
  46
  47 Standard PowerISA Integer registers are aliased to some of the SV integer registers:
  48
  49 | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register |
  50 |----------------------|-------------------------|----------------------|-------------------------|----------------------|-------------------------|----------------------|-------------------------|
  51 | R0                   | SVR0_00                 | R8                   | SVR8_00                 | R16                  | SVR16_00                | R24                  | SVR24_00                |
  52 |                      | SVR0_01                 |                      | SVR8_01                 |                      | SVR16_01                |                      | SVR24_01                |
  53 |                      | SVR0_10                 |                      | SVR8_10                 |                      | SVR16_10                |                      | SVR24_10                |
  54 |                      | SVR0_11                 |                      | SVR8_11                 |                      | SVR16_11                |                      | SVR24_11                |
  55 | R1                   | SVR1_00                 | R9                   | SVR9_00                 | R17                  | SVR17_00                | R25                  | SVR25_00                |
  56 |                      | SVR1_01                 |                      | SVR9_01                 |                      | SVR17_01                |                      | SVR25_01                |
  57 |                      | SVR1_10                 |                      | SVR9_10                 |                      | SVR17_10                |                      | SVR25_10                |
  58 |                      | SVR1_11                 |                      | SVR9_11                 |                      | SVR17_11                |                      | SVR25_11                |
  59 | R2                   | SVR2_00                 | R10                  | SVR10_00                | R18                  | SVR18_00                | R26                  | SVR26_00                |
  60 |                      | SVR2_01                 |                      | SVR10_01                |                      | SVR18_01                |                      | SVR26_01                |
  61 |                      | SVR2_10                 |                      | SVR10_10                |                      | SVR18_10                |                      | SVR26_10                |
  62 |                      | SVR2_11                 |                      | SVR10_11                |                      | SVR18_11                |                      | SVR26_11                |
  63 | R3                   | SVR3_00                 | R11                  | SVR11_00                | R19                  | SVR19_00                | R27                  | SVR27_00                |
  64 |                      | SVR3_01                 |                      | SVR11_01                |                      | SVR19_01                |                      | SVR27_01                |
  65 |                      | SVR3_10                 |                      | SVR11_10                |                      | SVR19_10                |                      | SVR27_10                |
  66 |                      | SVR3_11                 |                      | SVR11_11                |                      | SVR19_11                |                      | SVR27_11                |
  67 | R4                   | SVR4_00                 | R12                  | SVR12_00                | R20                  | SVR20_00                | R28                  | SVR28_00                |
  68 |                      | SVR4_01                 |                      | SVR12_01                |                      | SVR20_01                |                      | SVR28_01                |
  69 |                      | SVR4_10                 |                      | SVR12_10                |                      | SVR20_10                |                      | SVR28_10                |
  70 |                      | SVR4_11                 |                      | SVR12_11                |                      | SVR20_11                |                      | SVR28_11                |
  71 | R5                   | SVR5_00                 | R13                  | SVR13_00                | R21                  | SVR21_00                | R29                  | SVR29_00                |
  72 |                      | SVR5_01                 |                      | SVR13_01                |                      | SVR21_01                |                      | SVR29_01                |
  73 |                      | SVR5_10                 |                      | SVR13_10                |                      | SVR21_10                |                      | SVR29_10                |
  74 |                      | SVR5_11                 |                      | SVR13_11                |                      | SVR21_11                |                      | SVR29_11                |
  75 | R6                   | SVR6_00                 | R14                  | SVR14_00                | R22                  | SVR22_00                | R30                  | SVR30_00                |
  76 |                      | SVR6_01                 |                      | SVR14_01                |                      | SVR22_01                |                      | SVR30_01                |
  77 |                      | SVR6_10                 |                      | SVR14_10                |                      | SVR22_10                |                      | SVR30_10                |
  78 |                      | SVR6_11                 |                      | SVR14_11                |                      | SVR22_11                |                      | SVR30_11                |
  79 | R7                   | SVR7_00                 | R15                  | SVR15_00                | R23                  | SVR23_00                | R31                  | SVR31_00                |
  80 |                      | SVR7_01                 |                      | SVR15_01                |                      | SVR23_01                |                      | SVR31_01                |
  81 |                      | SVR7_10                 |                      | SVR15_10                |                      | SVR23_10                |                      | SVR31_10                |
  82 |                      | SVR7_11                 |                      | SVR15_11                |                      | SVR23_11                |                      | SVR31_11                |
  83
  84 ## Floating-Point Registers
  85
  86 Standard PowerISA floating-point and VSX registers are aliased to some of the SV floating-point registers:
  87
  88 | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register |
  89 |-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|
  90 | FPR\[0\]        | VSR\[0\]\.dword\[0\]  | SVFR0\_00          | FPR\[16\]       | VSR\[16\]\.dword\[0\] | SVFR16\_00         |
  91 |                 | VSR\[0\]\.dword\[1\]  | SVFR0\_01          |                 | VSR\[16\]\.dword\[1\] | SVFR16\_01         |
  92 |                 | VSR\[32\]\.dword\[0\] | SVFR0\_10          |                 | VSR\[48\]\.dword\[0\] | SVFR16\_10         |
  93 |                 | VSR\[32\]\.dword\[1\] | SVFR0\_11          |                 | VSR\[48\]\.dword\[1\] | SVFR16\_11         |
  94 | FPR\[1\]        | VSR\[1\]\.dword\[0\]  | SVFR1\_00          | FPR\[17\]       | VSR\[17\]\.dword\[0\] | SVFR17\_00         |
  95 |                 | VSR\[1\]\.dword\[1\]  | SVFR1\_01          |                 | VSR\[17\]\.dword\[1\] | SVFR17\_01         |
  96 |                 | VSR\[33\]\.dword\[0\] | SVFR1\_10          |                 | VSR\[49\]\.dword\[0\] | SVFR17\_10         |
  97 |                 | VSR\[33\]\.dword\[1\] | SVFR1\_11          |                 | VSR\[49\]\.dword\[1\] | SVFR17\_11         |
  98 | FPR\[2\]        | VSR\[2\]\.dword\[0\]  | SVFR2\_00          | FPR\[18\]       | VSR\[18\]\.dword\[0\] | SVFR18\_00         |
  99 |                 | VSR\[2\]\.dword\[1\]  | SVFR2\_01          |                 | VSR\[18\]\.dword\[1\] | SVFR18\_01         |
 100 |                 | VSR\[34\]\.dword\[0\] | SVFR2\_10          |                 | VSR\[50\]\.dword\[0\] | SVFR18\_10         |
 101 |                 | VSR\[34\]\.dword\[1\] | SVFR2\_11          |                 | VSR\[50\]\.dword\[1\] | SVFR18\_11         |
 102 | FPR\[3\]        | VSR\[3\]\.dword\[0\]  | SVFR3\_00          | FPR\[19\]       | VSR\[19\]\.dword\[0\] | SVFR19\_00         |
 103 |                 | VSR\[3\]\.dword\[1\]  | SVFR3\_01          |                 | VSR\[19\]\.dword\[1\] | SVFR19\_01         |
 104 |                 | VSR\[35\]\.dword\[0\] | SVFR3\_10          |                 | VSR\[51\]\.dword\[0\] | SVFR19\_10         |
 105 |                 | VSR\[35\]\.dword\[1\] | SVFR3\_11          |                 | VSR\[51\]\.dword\[1\] | SVFR19\_11         |
 106 | FPR\[4\]        | VSR\[4\]\.dword\[0\]  | SVFR4\_00          | FPR\[20\]       | VSR\[20\]\.dword\[0\] | SVFR20\_00         |
 107 |                 | VSR\[4\]\.dword\[1\]  | SVFR4\_01          |                 | VSR\[20\]\.dword\[1\] | SVFR20\_01         |
 108 |                 | VSR\[36\]\.dword\[0\] | SVFR4\_10          |                 | VSR\[52\]\.dword\[0\] | SVFR20\_10         |
 109 |                 | VSR\[36\]\.dword\[1\] | SVFR4\_11          |                 | VSR\[52\]\.dword\[1\] | SVFR20\_11         |
 110 | FPR\[5\]        | VSR\[5\]\.dword\[0\]  | SVFR5\_00          | FPR\[21\]       | VSR\[21\]\.dword\[0\] | SVFR21\_00         |
 111 |                 | VSR\[5\]\.dword\[1\]  | SVFR5\_01          |                 | VSR\[21\]\.dword\[1\] | SVFR21\_01         |
 112 |                 | VSR\[37\]\.dword\[0\] | SVFR5\_10          |                 | VSR\[53\]\.dword\[0\] | SVFR21\_10         |
 113 |                 | VSR\[37\]\.dword\[1\] | SVFR5\_11          |                 | VSR\[53\]\.dword\[1\] | SVFR21\_11         |
 114 | FPR\[6\]        | VSR\[6\]\.dword\[0\]  | SVFR6\_00          | FPR\[22\]       | VSR\[22\]\.dword\[0\] | SVFR22\_00         |
 115 |                 | VSR\[6\]\.dword\[1\]  | SVFR6\_01          |                 | VSR\[22\]\.dword\[1\] | SVFR22\_01         |
 116 |                 | VSR\[38\]\.dword\[0\] | SVFR6\_10          |                 | VSR\[54\]\.dword\[0\] | SVFR22\_10         |
 117 |                 | VSR\[38\]\.dword\[1\] | SVFR6\_11          |                 | VSR\[54\]\.dword\[1\] | SVFR22\_11         |
 118 | FPR\[7\]        | VSR\[7\]\.dword\[0\]  | SVFR7\_00          | FPR\[23\]       | VSR\[23\]\.dword\[0\] | SVFR23\_00         |
 119 |                 | VSR\[7\]\.dword\[1\]  | SVFR7\_01          |                 | VSR\[23\]\.dword\[1\] | SVFR23\_01         |
 120 |                 | VSR\[39\]\.dword\[0\] | SVFR7\_10          |                 | VSR\[55\]\.dword\[0\] | SVFR23\_10         |
 121 |                 | VSR\[39\]\.dword\[1\] | SVFR7\_11          |                 | VSR\[55\]\.dword\[1\] | SVFR23\_11         |
 122 | FPR\[8\]        | VSR\[8\]\.dword\[0\]  | SVFR8\_00          | FPR\[24\]       | VSR\[24\]\.dword\[0\] | SVFR24\_00         |
 123 |                 | VSR\[8\]\.dword\[1\]  | SVFR8\_01          |                 | VSR\[24\]\.dword\[1\] | SVFR24\_01         |
 124 |                 | VSR\[40\]\.dword\[0\] | SVFR8\_10          |                 | VSR\[56\]\.dword\[0\] | SVFR24\_10         |
 125 |                 | VSR\[40\]\.dword\[1\] | SVFR8\_11          |                 | VSR\[56\]\.dword\[1\] | SVFR24\_11         |
 126 | FPR\[9\]        | VSR\[9\]\.dword\[0\]  | SVFR9\_00          | FPR\[25\]       | VSR\[25\]\.dword\[0\] | SVFR25\_00         |
 127 |                 | VSR\[9\]\.dword\[1\]  | SVFR9\_01          |                 | VSR\[25\]\.dword\[1\] | SVFR25\_01         |
 128 |                 | VSR\[41\]\.dword\[0\] | SVFR9\_10          |                 | VSR\[57\]\.dword\[0\] | SVFR25\_10         |
 129 |                 | VSR\[41\]\.dword\[1\] | SVFR9\_11          |                 | VSR\[57\]\.dword\[1\] | SVFR25\_11         |
 130 | FPR\[10\]       | VSR\[10\]\.dword\[0\] | SVFR10\_00         | FPR\[26\]       | VSR\[26\]\.dword\[0\] | SVFR26\_00         |
 131 |                 | VSR\[10\]\.dword\[1\] | SVFR10\_01         |                 | VSR\[26\]\.dword\[1\] | SVFR26\_01         |
 132 |                 | VSR\[42\]\.dword\[0\] | SVFR10\_10         |                 | VSR\[58\]\.dword\[0\] | SVFR26\_10         |
 133 |                 | VSR\[42\]\.dword\[1\] | SVFR10\_11         |                 | VSR\[58\]\.dword\[1\] | SVFR26\_11         |
 134 | FPR\[11\]       | VSR\[11\]\.dword\[0\] | SVFR11\_00         | FPR\[27\]       | VSR\[27\]\.dword\[0\] | SVFR27\_00         |
 135 |                 | VSR\[11\]\.dword\[1\] | SVFR11\_01         |                 | VSR\[27\]\.dword\[1\] | SVFR27\_01         |
 136 |                 | VSR\[43\]\.dword\[0\] | SVFR11\_10         |                 | VSR\[59\]\.dword\[0\] | SVFR27\_10         |
 137 |                 | VSR\[43\]\.dword\[1\] | SVFR11\_11         |                 | VSR\[59\]\.dword\[1\] | SVFR27\_11         |
 138 | FPR\[12\]       | VSR\[12\]\.dword\[0\] | SVFR12\_00         | FPR\[28\]       | VSR\[28\]\.dword\[0\] | SVFR28\_00         |
 139 |                 | VSR\[12\]\.dword\[1\] | SVFR12\_01         |                 | VSR\[28\]\.dword\[1\] | SVFR28\_01         |
 140 |                 | VSR\[44\]\.dword\[0\] | SVFR12\_10         |                 | VSR\[60\]\.dword\[0\] | SVFR28\_10         |
 141 |                 | VSR\[44\]\.dword\[1\] | SVFR12\_11         |                 | VSR\[60\]\.dword\[1\] | SVFR28\_11         |
 142 | FPR\[13\]       | VSR\[13\]\.dword\[0\] | SVFR13\_00         | FPR\[29\]       | VSR\[29\]\.dword\[0\] | SVFR29\_00         |
 143 |                 | VSR\[13\]\.dword\[1\] | SVFR13\_01         |                 | VSR\[29\]\.dword\[1\] | SVFR29\_01         |
 144 |                 | VSR\[45\]\.dword\[0\] | SVFR13\_10         |                 | VSR\[61\]\.dword\[0\] | SVFR29\_10         |
 145 |                 | VSR\[45\]\.dword\[1\] | SVFR13\_11         |                 | VSR\[61\]\.dword\[1\] | SVFR29\_11         |
 146 | FPR\[14\]       | VSR\[14\]\.dword\[0\] | SVFR14\_00         | FPR\[30\]       | VSR\[30\]\.dword\[0\] | SVFR30\_00         |
 147 |                 | VSR\[14\]\.dword\[1\] | SVFR14\_01         |                 | VSR\[30\]\.dword\[1\] | SVFR30\_01         |
 148 |                 | VSR\[46\]\.dword\[0\] | SVFR14\_10         |                 | VSR\[62\]\.dword\[0\] | SVFR30\_10         |
 149 |                 | VSR\[46\]\.dword\[1\] | SVFR14\_11         |                 | VSR\[62\]\.dword\[1\] | SVFR30\_11         |
 150 | FPR\[15\]       | VSR\[15\]\.dword\[0\] | SVFR15\_00         | FPR\[31\]       | VSR\[31\]\.dword\[0\] | SVFR31\_00         |
 151 |                 | VSR\[15\]\.dword\[1\] | SVFR15\_01         |                 | VSR\[31\]\.dword\[1\] | SVFR31\_01         |
 152 |                 | VSR\[47\]\.dword\[0\] | SVFR15\_10         |                 | VSR\[63\]\.dword\[0\] | SVFR31\_10         |
 153 |                 | VSR\[47\]\.dword\[1\] | SVFR15\_11         |                 | VSR\[63\]\.dword\[1\] | SVFR31\_11         |
 154
 155
 156 # Operation
 157
 158 ## CR fields as inputs/outputs of vector operations
 159
 160 When vectorized, the CR inputs/outputs are read/written to 4-bit CR fields
 161 starting from CR6 and incrementing from there. If CR63 is reached, the next CR
 162 field used wraps around to CR0, then incrementing from there.
 163
 164 CR6 was chosen to balance avoiding needing to save CR2-CR4 (which are
 165 callee-saved) just to use SV vectors with VL <= 61 as well as having the first
 166 few used CR fields readily accessible to standard CR instructions and branches.
 167 Additionally, CR6 is used as the implicit result of a OpenPower ISA v3.1
 168 standard vector instruction with Rc=1.
 169
 170 # Forms
 171
 172 ## SVP64-A-FORM
 173
 174 Suffix is an A-FORM Instruction.
 175
 176 Prefix Fields:
 177 |  | PO (0:5) |  |  |  |
 178 |--|----------|--|--|--|
 179 |  | 1        |  |  |  |
 180
 181 TBD