openpower/sv/svp_rewrite/svp64.mdwn

   1 # Rewrite of SVP64 for OpenPower ISA v3.1
   2
   3 The plan is to create an encoding for SVP64, then to create an encoding for
   4 SVP48, then to reorganize them both to improve field overlap, reducing the
   5 amount of decoder hardware necessary.
   6
   7 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB and
   8 counting up as you move to the LSB end). All bit ranges are inclusive (so
   9 `4:6` means bits 4, 5, and 6).
  10
  11 64-bit instructions are split into two 32-bit words, the prefix and the suffix. The prefix always comes before the suffix in PC order.
  12
  13 ## Prefix Opcode Map (64-bit instruction encoding) (prefix bits 6:11)
  14
  15 (shows both PowerISA v3.1 instructions as well as new SVP instructions; empty spaces are yet-to-be-allocated Illegal Instructions)
  16
  17 | bits 6:11 | ---000   | ---001     | ---010   | ---011   | ---100   | ---101   | ---110   | ---111   |
  18 |-----------|----------|------------|----------|----------|----------|----------|----------|----------|
  19 | 000---    | 8LS-form | 8LS-form   | 8LS-form | 8LS-form | 8LS-form | 8LS-form | 8LS-form | 8LS-form |
  20 | 001---    |          |            |          |          |          |          |          |          |
  21 | 010---    | 8RR-form |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  22 | 011---    |          |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  23 | 100---    | MLS-form | MLS-form   | MLS-form | MLS-form | MLS-form | MLS-form | MLS-form | MLS-form |
  24 | 101---    |          |            |          |          |          |          |          |          |
  25 | 110---    | MRR-form |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  26 | 111---    |          | MMIRR-form |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
  27
  28 ## Prefix Fields
  29
  30 | Prefix Field Name   | Field bits | Constant Value | Description                            |
  31 |---------------------|------------|----------------|----------------------------------------|
  32 | PO (Primary Opcode) | `0:5`      | `1`            | Indicates this is a 64-bit instruction |
  33 | TBD                 | `6`        |                |                                        |
  34 | SVP64_7             | `7`        | `1`            | Indicates this is a SVP64 instruction  |
  35 | TBD                 | `8`        |                |                                        |
  36 | SVP64_9             | `9`        | `1`            | Indicates this is a SVP64 instruction  |
  37 | TBD                 | `10:31`    |                |                                        |
  38
  39 TBD