1 ## GPR Ternary Logic Immediate
3 Add this section to Book I 3.3.13
7 | 0-5 | 6-10 | 11-15 | 16-20 | 21-28 | 29-30 | 31 | Form |
8 |-----|------|-------|-------|-------|-------|----|----------|
9 | PO | RT | RA | RB | TLI | XO | Rc | TLI-Form |
11 * `ternlogi RT, RA, RB, TLI` (`Rc=0`)
12 * `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
17 result <- (~RT & ~RA & ~RB & TLI[0]*64) | # 64 copies of TLI[0]
18 (~RT & ~RA & RB & TLI[1]*64) | # ...
19 (~RT & RA & ~RB & TLI[2]*64) |
20 (~RT & RA & RB & TLI[3]*64) |
21 ( RT & ~RA & ~RB & TLI[4]*64) |
22 ( RT & ~RA & RB & TLI[5]*64) |
23 ( RT & RA & ~RB & TLI[6]*64) | # ...
24 ( RT & RA & RB & TLI[7]*64) # 64 copies of TLI[7]
28 For each integer value i, 0 to 63, do the following.
31 Let j be the value of the concatenation of the
32 contents of bit i of RT, bit i of RB, bit i of RT.
33 The value of bit j of TLI is placed into bit i of RT.
35 See Table 145, "xxeval(A, B, C, TLI) Equivalent
36 Functions," on page 968 for the equivalent function
37 evaluated by this instruction for any given value of TLI.
40 *Programmer's Note: this is a Read-Modify-Write instruction on RT.
41 A simple copy instruction may be used to achieve the effect of
42 3-in 1-out. The copy instruction should come immediately before
43 `ternlogi` so that hardware may optionally Macro-Op Fuse them*
45 *Programmer's note: This instruction is useful when combined with Matrix REMAP
46 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
47 applications in Computer Science.*
49 Special registers altered:
59 ## Condition Register Ternary Logic Immediate
61 Add this section to Book I 2.5.1
65 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form |
66 |----|----|----|-----|-----|-----|-----|-----|---|----------|
67 | PO | BF | msk|BFA | msk | BFB | TLI | XO |TLI| CRB-Form |
69 * `crternlogi BF, BFA, BFB, BFC, TLI, msk`
74 a <- CR[4*BF+32:4*BF+35]
75 b <- CR[4*BFA+32:4*BFA+35]
76 c <- CR[4*BFB+32:4*BFB+35]
77 ternary <- (~a & ~b & ~c & TLI[0]*4) | # 4 copies of TLI[0]
78 (~a & ~b & c & TLI[1]*4) | # 4 copies of TLI[1]
79 (~a & b & ~c & TLI[2]*4) | # ...
80 (~a & b & c & TLI[3]*4) |
81 ( a & ~b & ~c & TLI[4]*4) |
82 ( a & ~b & c & TLI[5]*4) |
83 ( a & b & ~c & TLI[6]*4) | # ...
84 ( a & b & c & TLI[7]*4)) # 4 copies of TLI[7]
87 CR[4*BF+32+i] <- ternary[i]
90 For each integer value i, 0 to 3, do the following.
93 Let j be the value of the concatenation of the
94 contents of bit i of CR Field BF, bit i of CR Field BFA,
95 bit i of CR Field BFB.
97 If bit i of msk is set to 1 then the value of bit j of TLI
98 is placed into bit i of CR Field BF.
100 Otherwise, if bit i of msk is a zero then bit i of
101 CR Field BF is unchanged.
103 See Table 145, "xxeval(A, B, C, TLI) Equivalent
104 Functions," on page 968 for the equivalent function
105 evaluated by this instruction for any given value of TLI.
108 If `msk` is zero an Illegal Instruction trap is raised.
110 *Programmer's Note: this instruction is a "masked" overwrite on CR Field
111 BF. For each bit set in msk a Write is performed but for each bit clear
112 in msk the corresponding bit of BF is preserved. Overall this makes
113 crbinlog a conditionally Read-Modify-Write instruction on CR Field BF.
114 A simple copy instruction may be used to achieve the effect of
115 3-in 1-out. The copy instruction should come immediately before
116 `crternlogi` so that hardware may optionally Macro-Op Fuse them*
118 Special registers altered:
128 ## GPR Dynamic Binary Logic
130 Add this section to Book I 3.3.13
134 | 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26 | 27-31 | Form |
135 |-----|------|-------|-------|-------|----|-------|---------|
136 | PO | RT | RA | RB | RC | nh | XO | VA-Form |
138 * `binlog RT, RA, RB, RC, nh`
143 if nh = 1 then lut <- (RC)[56:59]
144 else lut <- (RC)[60:63]
145 result <- (~RA & ~RB & lut[0]*64) |
146 (~RA & RB & lut[1]*64) |
147 ( RA & ~RB & lut[2]*64) |
148 ( RA & RB & lut[3]*64))
152 For each integer value i, 0 to 63, do the following.
155 If nh contains a 0, let lut be the four LSBs of RC
156 (bits 60 to 63). Otherwise let lut be the next
157 four LSBs of RC (bits 56 to 59).
159 Let j be the value of the concatenation of the
160 contents of bit i of RT with bit i of RB.
162 The value of bit j of lut is placed into bit i of RT.
165 Special registers altered:
171 **Programmer's Note**:
173 Dynamic (non-immediate-based) Ternary Logic, suitable for FPGA-style LUT3
174 dynamic lookups and for JIT runtime acceleration, may be emulated by
175 appropriate combination of `binlog` and `ternlogi`, using the `nh`
176 (next half) operand to select first and second nibble:
179 # compute r3 = ternlog(r4, r5, r6, table=r7)
180 # compute the values for when r6[i] = 0:
181 binlog r3, r4, r5, r7, 0 # takes look-up-table from LSB 4 bits
182 # compute the values for when r6[i] = 1:
183 binlog r4, r4, r5, r7, 1 # takes look-up-table from second-to-LSB 4 bits
184 # mux the two results together: r3 = (r3 & ~r6) | (r4 & r6)
185 ternlogi r3, r4, r6, 0b11011000
192 ## Condition Register Field Dynamic Binary Logic
194 Add this section to Book I 2.5.1
198 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form |
199 |----|----|----|-----|-----|-----|-----|-----|---|----------|
200 | PO | BF | msk|BFA | msk | BFB | // | XO |// | CRB-Form |
202 * `crbinlog BF, BFA, BFB, msk`
207 a <- CR[4*BF+32:4*BFA+35]
208 b <- CR[4*BFA+32:4*BFA+35]
209 lut <- CR[4*BFB+32:4*BFB+35]
210 binary <- (~a & ~b & lut[0]*4) |
211 (~a & b & lut[1]*4) |
212 ( a & ~b & lut[2]*4) |
216 CR[4*BF+32+i] <- binary[i]
219 For each integer value i, 0 to 3, do the following.
222 Let j be the value of the concatenation of the
223 contents of bit i of CR Field BF with bit i of CR Field BFA.
225 If bit i of msk is set to 1 then the value of bit j of
226 CR Field BFB is placed into bit i of CR Field BF.
228 Otherwise, if bit i of msk is a zero then bit i of
229 CR Field BF is unchanged.
232 If `msk` is zero an Illegal Instruction trap is raised.
234 Special registers altered:
240 *Programmer's Note: just as with binlut and ternlogi, a pair
241 of crbinlog instructions followed by a merging crternlogi may
242 be deployed to synthesise dynamic ternary (LUT3) CR Field
245 *Programmer's Note: this instruction is a "masked" overwrite on CR
246 Field BF. For each bit set in `msk` a Write is performed
247 but for each bit clear in `msk` the corresponding bit of BF is
248 preserved. Overall this makes `crbinlog` a conditionally
249 Read-Modify-Write instruction on CR Field BF.
250 A simple copy instruction may be used to achieve the effect of
251 3-in 1-out. The copy instruction should come immediately before
252 `crternlogi` so that hardware may optionally Macro-Op Fuse them*