1 ## GPR Ternary Logic Immediate
3 Add this section to Book I 3.3.13
7 * `ternlogi RT, RA, RB, TLI` (`Rc=0`)
8 * `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
10 | 0-5 | 6-10 | 11-15 | 16-20 | 21-28 | 29-30 | 31 | Form |
11 |-----|------|-------|-------|-------|-------|----|----------|
12 | PO | RT | RA | RB | TLI | XO | Rc | TLI-Form |
17 result <- (~RT & ~RA & ~RB & TLI[0]*64) | # 64 copies of TLI[0]
18 (~RT & ~RA & RB & TLI[1]*64) | # ...
19 (~RT & RA & ~RB & TLI[2]*64) |
20 (~RT & RA & RB & TLI[3]*64) |
21 ( RT & ~RA & ~RB & TLI[4]*64) |
22 ( RT & ~RA & RB & TLI[5]*64) |
23 ( RT & RA & ~RB & TLI[6]*64) | # ...
24 ( RT & RA & RB & TLI[7]*64) # 64 copies of TLI[7]
28 For each integer value i, 0 to 63, do the following.
31 Let j be the value of the concatenation of the
32 contents of bit i of RT, bit i of RB, bit i of RT.
33 The value of bit j of TLI is placed into bit i of RT.
35 See Table 145, "xxeval(A, B, C, TLI) Equivalent
36 Functions," on page 968 for the equivalent function
37 evaluated by this instruction for any given value of TLI.
40 *Programmer's Note: this is a Read-Modify-Write instruction on RT.*
42 *Programmer's note: This instruction is useful when combined with Matrix REMAP
43 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
44 applications in Computer Science.*
46 Special registers altered:
56 ## Condition Register Ternary Logic Immediate
58 Add this section to Book I 2.5.1
62 * `crternlogi BF, BFA, BFB, BFC, TLI, msk`
64 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form |
65 |----|----|----|-----|-----|-----|-----|-----|---|----------|
66 | PO | BF | msk|BFA | msk | BFB | TLI | XO |TLI| CRB-Form |
71 a <- CR[4*BF+32:4*BF+35]
72 b <- CR[4*BFA+32:4*BFA+35]
73 c <- CR[4*BFB+32:4*BFB+35]
74 ternary <- (~a & ~b & ~c & TLI[0]*4) | # 4 copies of TLI[0]
75 (~a & ~b & c & TLI[1]*4) | # 4 copies of TLI[1]
76 (~a & b & ~c & TLI[2]*4) | # ...
77 (~a & b & c & TLI[3]*4) |
78 ( a & ~b & ~c & TLI[4]*4) |
79 ( a & ~b & c & TLI[5]*4) |
80 ( a & b & ~c & TLI[6]*4) | # ...
81 ( a & b & c & TLI[7]*4)) # 4 copies of TLI[7]
84 CR[4*BF+32+i] <- ternary[i]
87 For each integer value i, 0 to 3, do the following.
90 Let j be the value of the concatenation of the
91 contents of bit i of CR Field BF, bit i of CR Field BFA,
92 bit i of CR Field BFB.
94 If bit i of msk is set to 1 then the value of bit j of TLI
95 is placed into bit i of CR Field BF.
97 Otherwise, if bit i of msk is a zero then bit i of
98 CR Field BF is unchanged.
100 See Table 145, "xxeval(A, B, C, TLI) Equivalent
101 Functions," on page 968 for the equivalent function
102 evaluated by this instruction for any given value of TLI.
105 If `msk` is zero an Illegal Instruction trap is raised.
107 *Programmer's Note: this instruction is a "masked" overwrite on CR Field
108 BF. For each bit set in msk a Write is performed but for each bit clear
109 in msk the corresponding bit of BF is preserved. Overall this makes
110 crbinlog a conditionally Read-Modify-Write instruction on CR Field BF*
112 Special registers altered:
122 ## GPR Dynamic Binary Logic
124 Add this section to Book I 3.3.13
128 * `binlog RT, RA, RB, RC, nh`
130 | 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26 | 27-31 | Form |
131 |-----|------|-------|-------|-------|----|-------|---------|
132 | PO | RT | RA | RB | RC | nh | XO | VA-Form |
137 if nh = 1 then lut <- (RC)[56:59]
138 else lut <- (RC)[60:63]
139 result <- (~RA & ~RB & lut[0]*64) |
140 (~RA & RB & lut[1]*64) |
141 ( RA & ~RB & lut[2]*64) |
142 ( RA & RB & lut[3]*64))
146 For each integer value i, 0 to 63, do the following.
149 If nh contains a 0, let lut be the four LSBs of RC
150 (bits 60 to 63). Otherwise let lut be the next
151 four LSBs of RC (bits 56 to 59).
153 Let j be the value of the concatenation of the
154 contents of bit i of RT with bit i of RB.
156 The value of bit j of lut is placed into bit i of RT.
159 Special registers altered:
165 **Programmer's Note**:
167 Dynamic (non-immediate-based) Ternary Logic, suitable for FPGA-style LUT3
168 dynamic lookups and for JIT runtime acceleration, may be emulated by
169 appropriate combination of `binlog` and `ternlogi`, using the `nh`
170 (next half) operand to select first and second nibble:
173 # compute r3 = ternlog(r4, r5, r6, table=r7)
174 # compute the values for when r6[i] = 0:
175 binlog r3, r4, r5, r7, 0 # takes look-up-table from LSB 4 bits
176 # compute the values for when r6[i] = 1:
177 binlog r4, r4, r5, r7, 1 # takes look-up-table from second-to-LSB 4 bits
178 # mux the two results together: r3 = (r3 & ~r6) | (r4 & r6)
179 ternlogi r3, r4, r6, 0b11011000
186 ## Condition Register Field Dynamic Binary Logic
188 Add this section to Book I 2.5.1
192 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31| Form |
193 |----|----|----|-----|-----|-----|-----|-----|---|----------|
194 | PO | BF | msk|BFA | msk | BFB | // | XO |// | CRB-Form |
199 a <- CR[4*BF+32:4*BFA+35]
200 b <- CR[4*BFA+32:4*BFA+35]
201 lut <- CR[4*BFB+32:4*BFB+35]
202 binary <- (~a & ~b & lut[0]*4) |
203 (~a & b & lut[1]*4) |
204 ( a & ~b & lut[2]*4) |
208 CR[4*BF+32+i] <- binary[i]
211 For each integer value i, 0 to 3, do the following.
214 Let j be the value of the concatenation of the
215 contents of bit i of CR Field BF with bit i of CR Field BFA.
217 If bit i of msk is set to 1 then the value of bit j of
218 CR Field BFB is placed into bit i of CR Field BF.
220 Otherwise, if bit i of msk is a zero then bit i of
221 CR Field BF is unchanged.
224 If `msk` is zero an Illegal Instruction trap is raised.
226 Special registers altered:
232 *Programmer's Note: just as with binlut and ternlogi, a pair
233 of crbinlog instructions followed by a merging crternlogi may
234 be deployed to synthesise dynamic ternary (LUT3) CR Field
237 *Programmer's Note: this instruction is a "masked" overwrite on CR
238 Field BF. For each bit set in `msk` a Write is performed
239 but for each bit clear in `msk` the corresponding bit of BF is
240 preserved. Overall this makes `crbinlog` a conditionally
241 Read-Modify-Write instruction on CR Field BF*