1 * <https://bugs.libre-soc.org/show_bug.cgi?id=1074>
2 * <https://libre-soc.org/openpower/sv/biginteger/> for format and
3 information about implicit RS/FRS
4 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_dct.py;hb=HEAD>
5 * [[openpower/isa/svfparith]]
7 # [DRAFT] Twin Butterfly DCT Instruction(s)
9 The goal is to implement instructions that calculate the expression:
12 fdct_round_shift((a +/- b) * c)
15 For the single-coefficient butterfly instruction, and:
18 fdct_round_shift(a * c1 +/- b * c2)
21 For the double-coefficient butterfly instruction.
23 `fdct_round_shift` is defined as `ROUND_POWER_OF_TWO(x, 14)`
26 #define ROUND_POWER_OF_TWO(value, n) (((value) + (1 << ((n)-1))) >> (n))
29 These instructions are at the core of **ALL** FDCT calculations in many major video codecs, including -but not limited to- VP8/VP9, AV1, etc.
30 Arm includes special instructions to optimize these operations, although they are limited in precision: `vqrdmulhq_s16`/`vqrdmulhq_s32`.
32 The suggestion is to have a single instruction to calculate both values `((a + b) * c) >> N`, and `((a - b) * c) >> N`.
33 The instruction will run in accumulate mode, so in order to calculate the 2-coeff version one would just have to call the same instruction with different order a, b and a different constant c.
35 # [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
39 * maddsubrs RT,RA,SH,RB
47 prod1 <- MULS(RB, sum)[XLEN:(XLEN*2)-1]
48 prod2 <- MULS(RB, diff)[XLEN:(XLEN*2)-1]
49 res1 <- ROTL64(prod1, XLEN-n)
50 res2 <- ROTL64(prod2, XLEN-n)
51 m <- MASK(n, (XLEN-1))
54 smask1 <- ([signbit1]*XLEN) & ¬m
55 smask2 <- ([signbit2]*XLEN) & ¬m
56 s64_1 <- [0]*(XLEN-1) || signbit1
57 s64_2 <- [0]*(XLEN-1) || signbit2
58 RT <- (res1 & m | smask1) + s64_1
59 RS <- (res2 & m | smask2) + s64_2
62 Special Registers Altered:
68 Where we have added this variant in A-Form (defined in fields.txt):
72 |0 |6 |11 |16 |21 |26 |31 |
73 | PO | RT | RA | RB | SH | XO |Rc |
77 The instruction has been added to `minor_22.csv`:
80 ------01000,ALU,OP_MADDSUBRS,RT,CONST_SH,RB,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
84 # [DRAFT] Floating Twin Multiply-Add DCT [Single]
89 |0 |6 |11 |16 |21 |31 |
90 | PO | FRT | FRA | FRB | XO | Rc|
93 * fdmadds FRT,FRA,FRB (Rc=0)
94 * fdmadds. FRT,FRA,FRB (Rc=1)
99 FRS <- FPADD32(FRT, FRB)
100 sub <- FPSUB32(FRT, FRB)
101 FRT <- FPMUL32(FRA, sub)
104 Special Registers Altered:
113 # [DRAFT] Floating Multiply-Add FFT [Single]
118 |0 |6 |11 |16 |21 |31 |
119 | PO | FRT | FRA | FRB | XO | Rc|
122 * ffmadds FRT,FRA,FRB (Rc=0)
123 * ffmadds. FRT,FRA,FRB (Rc=1)
129 FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
130 FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)
133 Special Registers Altered: