3 # SV Vector Operations.
5 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
9 * Some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section.
10 * Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
11 * Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations. See [[sv/cr_int_predication]].
15 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions>
16 * <http://0x80.pl/notesen/2016-10-23-avx512-conflict-detection.html> conflictd example
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=213>
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=142> specialist vector ops
19 out of scope for this document
20 * [[simple_v_extension/specification/bitmanip]] previous version,
21 contains pseudocode for sof, sif, sbf
27 This is based on the AVX512 conflict detection instruction. Internally the logic is used to detect address conflicts in multi-issue LD/ST operations. Two arrays of values are given: the indices are compared and duplicates reported in a triangular fashion. the instruction may be used for histograms (computed in parallel)
29 input = [100, 100, 3, 100, 5, 100, 100, 3]
31 0b00000000, // Note: first element always zero
32 0b00000001, // 100 is present on #0
34 0b00000011, // 100 is present on #0 and #1
36 0b00001011, // 100 is present on #0, #1, #3
37 0b00011011, // .. and #4
38 0b00000100 // 3 is present on #2
45 if src1[i] == src2[j]:
50 Based on RVV vmiota. vmiota may be viewed as a cumulative variant of popcount, generating multiple results. successive iterations include more and more bits of the bitstream being tested.
52 When masked, only the bits not masked out are included in the count process.
56 Note that when RA=0 this indicates to test against all 1s, resulting in the instruction generating a vector sequence [0, 1, 2... VL-1]. This will be equivalent to RVV vid.m which is a pseudo-op, here (RA=0).
60 7 6 5 4 3 2 1 0 Element number
62 1 0 0 1 0 0 0 1 v2 contents
63 viota.m v4, v2 # Unmasked
64 2 2 2 1 1 1 1 0 v4 result
66 1 1 1 0 1 0 1 1 v0 contents
67 1 0 0 1 0 0 0 1 v2 contents
68 2 3 4 5 6 7 8 9 v4 contents
69 viota.m v4, v2, v0.t # Masked
70 1 1 1 5 1 7 1 0 v4 results
73 mask = RB ? iregs[RB] : 0b111111...1
74 val = RA ? iregs[RA] : 0b111111...1
77 testmask = (1<<i)-1 # only count below
78 to_test = val & testmask & mask
79 iregs[RT+i] = popcount(to_test)
81 a Vector CR-based version of the same, due to CRs being used for predication. This would use the same testing mechanism as branch: BO[0:2]
82 where bit 2 is inv, bits 0:1 select the bit of the CR.
84 def test_CR_bit(CR, BO):
85 return CR[BO[0:1]] == BO[2]
87 def iotacr(RT, BA, BO):
88 mask = get_src_predicate()
91 if mask & (1<<i) == 0: continue
93 if test_CR_bit(CR[i+BA], BO):
96 the variant of iotacr which is vidcr, this is not appropriate to have BA=0, plus, it is pointless to have it anyway. The integer version covers it, by not reading the int regfile at all.
100 These may all be viewed as suitable for fitting into a scalar bitmanip extension.
108 7 6 5 4 3 2 1 0 Bit index
110 1 0 0 1 0 1 0 0 v3 contents
112 0 0 0 0 0 0 1 1 v2 contents
114 1 0 0 1 0 1 0 1 v3 contents
118 0 0 0 0 0 0 0 0 v3 contents
122 1 1 0 0 0 0 1 1 RB vcontents
123 1 0 0 1 0 1 0 0 v3 contents
125 0 1 x x x x 1 1 v2 contents
127 The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1.
131 def sbf(rd, rs1, rs2):
133 # start setting if no predicate or if 1st predicate bit set
134 setting_mode = rs2 == x0 or (regs[rs2] & 1)
137 if rs2 != x0 and (regs[rs2] & bit):
141 if regs[rs1] & bit: # found a bit in rs1: stop setting rd
145 else if rs2 != x0: # searching mode
146 if (regs[rs2] & bit):
147 setting_mode = True # back into "setting" mode
152 The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.
158 7 6 5 4 3 2 1 0 Bit number
160 1 0 0 1 0 1 0 0 v3 contents
162 0 0 0 0 0 1 1 1 v2 contents
164 1 0 0 1 0 1 0 1 v3 contents
168 1 1 0 0 0 0 1 1 RB vcontents
169 1 0 0 1 0 1 0 0 v3 contents
171 1 1 x x x x 1 1 v2 contents
175 def sif(rd, rs1, rs2):
177 setting_mode = rs2 == x0 or (regs[rs2] & 1)
182 # only reenable when predicate in use, and bit valid
183 if !setting_mode && rs2 != x0:
184 if (regs[rs2] & bit):
185 # back into "setting" mode
191 if regs[rs1] & bit == 1:
195 # setting mode, search for 1
196 regs[rd] |= bit # always set during search
197 if regs[rs1] & bit: # found a bit in rs1:
199 # next loop starts skipping
206 The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.
212 7 6 5 4 3 2 1 0 Bit number
214 1 0 0 1 0 1 0 0 v3 contents
216 0 0 0 0 0 1 0 0 v2 contents
218 1 0 0 1 0 1 0 1 v3 contents
222 1 1 0 0 0 0 1 1 RB vcontents
223 1 1 0 1 0 1 0 0 v3 contents
225 0 1 x x x x 0 0 v2 content
229 def sof(rd, rs1, rs2):
231 setting_mode = rs2 == x0 or (regs[rs2] & 1)
236 # only reenable when predicate in use, and bit valid
237 if !setting_mode && rs2 != x0:
238 if (regs[rs2] & bit):
239 # back into "setting" mode
245 if regs[rs1] & bit == 1:
249 # setting mode, search for 1
250 if regs[rs1] & bit: # found a bit in rs1:
251 regs[rd] |= bit # only set when search succeeds
253 # next loop starts skipping
259 used not just for carry lookahead, also a special type of predication mask operation.
261 * <https://www.geeksforgeeks.org/carry-look-ahead-adder/>
262 * <https://media.geeksforgeeks.org/wp-content/uploads/digital_Logic6.png>
263 * <https://electronics.stackexchange.com/questions/20085/whats-the-difference-with-carry-look-ahead-generator-block-carry-look-ahead-ge>
264 * <https://i.stack.imgur.com/QSLKY.png>
265 * <https://stackoverflow.com/questions/27971757/big-integer-addition-code>
268 two versions: scalar int version and CR based version.
270 scalar int version acts as a scalar carry-propagate, reading XER.CA as input, P and G as regs, and taking a radix argument. the end bits go into XER.CA and CR0.ge
272 vector version takes CR0.so as carry in, stores in CR0.so and CR.ge end bits.
274 if zero (no propagation) then CR0.eq is zero
276 CR based version, TODO.