1 # SV Vector Operations.
3 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
7 * Some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section.
8 * Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
9 * Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations. See [[sv/cr_int_predication]].
13 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions>
14 * <http://0x80.pl/notesen/2016-10-23-avx512-conflict-detection.html> conflictd example
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=213>
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=142> specialist vector ops
17 out of scope for this document
18 * [[simple_v_extension/specification/bitmanip]] previous version,
19 contains pseudocode for sof, sif, sbf
25 This is based on the AVX512 conflict detection instruction. Internally the logic is used to detect address conflicts in multi-issue LD/ST operations. Two arrays of values are given: the indices are compared and duplicates reported in a triangular fashion. the instruction may be used for histograms (computed in parallel)
27 input = [100, 100, 3, 100, 5, 100, 100, 3]
29 0b00000000, // Note: first element always zero
30 0b00000001, // 100 is present on #0
32 0b00000011, // 100 is present on #0 and #1
34 0b00001011, // 100 is present on #0, #1, #3
35 0b00011011, // .. and #4
36 0b00000100 // 3 is present on #2
43 if src1[i] == src2[j]:
48 Based on RVV vmiota. vmiota may be viewed as a cumulative variant of popcount, generating multiple results. successive iterations include more and more bits of the bitstream being tested.
50 When masked, only the bits not masked out are included in the count process.
54 Note that when RA=0 this indicates to test against all 1s, resulting in the instruction generating a vector sequence [0, 1, 2... VL-1]. This will be equivalent to RVV vid.m which is a pseudo-op, here (RA=0).
58 7 6 5 4 3 2 1 0 Element number
60 1 0 0 1 0 0 0 1 v2 contents
61 viota.m v4, v2 # Unmasked
62 2 2 2 1 1 1 1 0 v4 result
64 1 1 1 0 1 0 1 1 v0 contents
65 1 0 0 1 0 0 0 1 v2 contents
66 2 3 4 5 6 7 8 9 v4 contents
67 viota.m v4, v2, v0.t # Masked
68 1 1 1 5 1 7 1 0 v4 results
71 mask = RB ? iregs[RB] : 0b111111...1
72 val = RA ? iregs[RA] : 0b111111...1
75 testmask = (1<<i)-1 # only count below
76 to_test = val & testmask & mask
77 iregs[RT+i] = popcount(to_test)
79 a Vector CR-based version of the same, due to CRs being used for predication. This would use the same testing mechanism as branch: BO[0:2]
80 where bit 2 is inv, bits 0:1 select the bit of the CR.
82 def test_CR_bit(CR, BO):
83 return CR[BO[0:1]] == BO[2]
85 def iotacr(RT, BA, BO):
86 mask = get_src_predicate()
89 if mask & (1<<i) == 0: continue
91 if test_CR_bit(CR[i+BA], BO):
94 the variant of iotacr which is vidcr, this is not appropriate to have BA=0, plus, it is pointless to have it anyway. The integer version covers it, by not reading the int regfile at all.
98 These may all be viewed as suitable for fitting into a scalar bitmanip extension.
106 7 6 5 4 3 2 1 0 Bit index
108 1 0 0 1 0 1 0 0 v3 contents
110 0 0 0 0 0 0 1 1 v2 contents
112 1 0 0 1 0 1 0 1 v3 contents
116 0 0 0 0 0 0 0 0 v3 contents
120 1 1 0 0 0 0 1 1 RB vcontents
121 1 0 0 1 0 1 0 0 v3 contents
123 0 1 x x x x 1 1 v2 contents
125 The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1.
129 def sbf(rd, rs1, rs2):
131 # start setting if no predicate or if 1st predicate bit set
132 setting_mode = rs2 == x0 or (regs[rs2] & 1)
135 if rs2 != x0 and (regs[rs2] & bit):
139 if regs[rs1] & bit: # found a bit in rs1: stop setting rd
143 else if rs2 != x0: # searching mode
144 if (regs[rs2] & bit):
145 setting_mode = True # back into "setting" mode
150 The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.
156 7 6 5 4 3 2 1 0 Bit number
158 1 0 0 1 0 1 0 0 v3 contents
160 0 0 0 0 0 1 1 1 v2 contents
162 1 0 0 1 0 1 0 1 v3 contents
166 1 1 0 0 0 0 1 1 RB vcontents
167 1 0 0 1 0 1 0 0 v3 contents
169 1 1 x x x x 1 1 v2 contents
173 def sif(rd, rs1, rs2):
175 setting_mode = rs2 == x0 or (regs[rs2] & 1)
180 # only reenable when predicate in use, and bit valid
181 if !setting_mode && rs2 != x0:
182 if (regs[rs2] & bit):
183 # back into "setting" mode
189 if regs[rs1] & bit == 1:
193 # setting mode, search for 1
194 regs[rd] |= bit # always set during search
195 if regs[rs1] & bit: # found a bit in rs1:
197 # next loop starts skipping
204 The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.
210 7 6 5 4 3 2 1 0 Bit number
212 1 0 0 1 0 1 0 0 v3 contents
214 0 0 0 0 0 1 0 0 v2 contents
216 1 0 0 1 0 1 0 1 v3 contents
220 1 1 0 0 0 0 1 1 RB vcontents
221 1 1 0 1 0 1 0 0 v3 contents
223 0 1 x x x x 0 0 v2 content
227 def sof(rd, rs1, rs2):
229 setting_mode = rs2 == x0 or (regs[rs2] & 1)
234 # only reenable when predicate in use, and bit valid
235 if !setting_mode && rs2 != x0:
236 if (regs[rs2] & bit):
237 # back into "setting" mode
243 if regs[rs1] & bit == 1:
247 # setting mode, search for 1
248 if regs[rs1] & bit: # found a bit in rs1:
249 regs[rd] |= bit # only set when search succeeds
251 # next loop starts skipping
257 * <https://media.geeksforgeeks.org/wp-content/uploads/digital_Logic6.png>
258 * <https://electronics.stackexchange.com/questions/20085/whats-the-difference-with-carry-look-ahead-generator-block-carry-look-ahead-ge>