1 # Simple-V Vectorisation for the OpenPOWER ISA
3 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
5 Fundamental design principles:
7 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
8 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
9 * Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions
10 (termed "preserving Program Order")
11 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
12 * Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
14 Advantages of these design principles:
16 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
17 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
18 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
19 * Completely wipes not just SIMD opcode proliferation off the
20 map but off of Vectorisation as well. No more separate Vector
23 Pages being developed and examples
26 * [[sv/masked_vector_chaining]]
28 * [[sv/example_dep_matrices]]
30 * [[sv/major_opcode_allocation]]
31 * [[opcode_regs_deduped]]
32 * [[sv/vector_swizzle]]
33 * [[sv/16_bit_compressed]]
34 * [[sv/toc_data_pointer]]
35 * [[sv/cr_int_predication]]