5 <img src="https://assets.amuniversal.com/7fada35026ca01393d3d005056a9545d" width="600" />
9 * <https://bugs.libre-soc.org/show_bug.cgi?id=213>
10 * <https://youtu.be/ZQ5hw9AwO1U> walkthrough video (19jun2022)
12 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
16 # Scalable Vectors for the Power ISA
18 SV is designed as a strict RISC-paradigm
19 Scalable Vector ISA for Hybrid 3D CPU GPU VPU workloads.
20 As such it brings features normally only found in Cray Supercomputers
21 (Cray-1, NEC SX-Aurora)
22 and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
23 a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
24 explicit Vector opcode exists in SV, at all**. It is suitable for
25 low-power Embedded and DSP Workloads as much as it is for power-efficient
28 Fundamental design principles:
30 * Taking the simplicity of the RISC paradigm and applying it strictly and
31 uniformly to create a Scalable Vector ISA.
32 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar
34 * Preserving the underlying scalar execution dependencies as if the
35 for-loop had been expanded as actual scalar instructions
36 (termed "preserving Program Order")
37 * Augments ("tags") existing instructions, providing Vectorisation
38 "context" rather than adding new instructions.
39 * Strictly does not interfere with or alter the non-Scalable Power ISA
41 * In the Prefix space, does not modify or deviate from the underlying
43 unless it provides significant performance or other advantage to do so
44 in the Vector space (dropping the "sticky" characteristics
45 of XER.SO and CR0.SO for example)
46 * Designed for Supercomputing: avoids creating significant sequential
47 dependency hazards, allowing standard
48 high performance superscalar multi-issue
49 micro-architectures to be leveraged.
50 * Divided into Compliancy Levels to reduce cost of implementation for
53 Advantages of these design principles:
55 * Simplicity of introduction and implementation on top of
56 the existing Power ISA without disruption.
57 * It is therefore easy to create a first (and sometimes only)
58 implementation as literally a for-loop in hardware, simulators, and
60 * Hardware Architects may understand and implement SV as being an
61 extra pipeline stage, inserted between decode and issue, that is
62 a simple for-loop issuing element-level sub-instructions.
63 * More complex HDL can be done by repeating existing scalar ALUs and
64 pipelines as blocks and leveraging existing Multi-Issue Infrastructure
65 * As (mostly) a high-level "context" that does not (significantly) deviate
66 from scalar Power ISA and, in its purest form being "a for loop around
67 scalar instructions", it is minimally-disruptive and consequently stands
68 a reasonable chance of broad community adoption and acceptance
69 * Completely wipes not just SIMD opcode proliferation off the
70 map (SIMD is O(N^6) opcode proliferation)
71 but off of Vectorisation ISAs as well. No more separate Vector
74 Comparative instruction count:
76 * ARM NEON SIMD: around 2,000 instructions, prerequisite: ARM Scalar.
77 * ARM SVE: around 4,000 instructions, prerequisite: NEON.
78 * ARM SVE2: around 1,000 instructions, prerequisite: SVE
79 * Intel AVX-512: around 4,000 instructions, prerequisite AVX, AVX2,
80 AVX-128 and AVX-256 which in turn critically rely on the rest of
81 x86, for a grand total of well over 10,000 instructions.
82 * RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
83 * SVP64: **five** instructions, 24-bit prefixing of
84 prerequisite SFS (150) or
85 SFFS (214) Compliancy Subsets
87 SV comprises several [[sv/compliancy_levels]] suited to Embedded, Energy
88 efficient High-Performance Compute, Distributed Computing and Advanced
89 Computational Supercomputing. The Compliancy Levels are arranged such
90 that even at the bare minimum Level, full Soft-Emulation of all
91 optional and future features is possible.
95 Pages being developed and examples
97 * [[sv/overview]] explaining the basics.
98 * [[sv/compliancy_levels]] for minimum subsets through to Advanced
100 * [[sv/implementation]] implementation planning and coordination
101 * [[sv/svp64]] contains the packet-format *only*, the [[svp64/appendix]]
102 contains explanations and further details
103 * [[sv/svp64_quirks]] things in SVP64 that slightly break the rules
104 or are not immediately apparent despite the RISC paradigm
105 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
108 - For condition register operations see [[sv/cr_ops]] - SVP64 Condition
109 Register ops: Guidelines
110 on Vectorisation of any v3.0B base operations which return
111 or modify a Condition Register bit or field.
112 - For LD/ST Modes, see [[sv/ldst]].
113 - For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch
114 behaviour: All/Some Vector CRs
115 - For arithmetic and logical, see [[sv/normal]]
116 - [[sv/mv.vec]] pack/unpack move to and from vec2/3/4,
117 actually an RM.EXTRA Mode and a [[sv/remap]] mode
119 Core SVP64 instructions:
121 * [[sv/setvl]] the Cray-style "Vector Length" instruction
122 * [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
123 * [[sv/svstep]] Key stepping instruction for Vertical-First Mode
125 *Please note: there are only five instructions in the whole of SV.
126 Beyond this point are additional **Scalar** instructions related to
127 specific workloads that have nothing to do with the SV Specification*
129 # Non-Simple-V Scalar instructions
131 **Additional Instructions for specific purposes (not SVP64)**
133 All of these instructions below have nothing to do with SV.
134 They are all entirely designed as Scalar instructions that, as
135 Scalar instructions, stand on their own merit. Considerable
136 lengths have been made to provide justifications for each of these
137 *Scalar* instructions.
139 Some of these Scalar instructions are specifically designed to make
140 Scalable Vector binaries more efficient, such
141 as the crweird group. Others are to bring the Scalar Power ISA
142 up-to-date within specific workloads,
143 such as a Javascript Rounding instruction. None of them are strictly
144 necessary but performance and power consumption may be (or, is already)
146 in certain workloads and use-cases without them.
150 * [[sv/mv.swizzle]] vec2/3/4 Swizzles (RGBA, XYZW) for 3D and CUDA.
151 designed as a Scalar instruction.
152 * [[sv/vector_ops]] scalar operations needed for supporting vectors
156 * [[sv/cr_int_predication]] instructions needed for effective predication
158 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
159 * [[sv/fclass]] detect class of FP numbers
160 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
161 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
162 * Twin targetted instructions (two registers out, one implicit, just like
164 Explanation of the rules for twin register targets
165 (implicit RS, FRS) explained in SVP64 [[svp64/appendix]]
166 - [[isa/svfixedarith]]
168 - [[sv/biginteger]] Operations that help with big arithmetic
169 * TODO: OpenPOWER adaptation [[openpower/transcendentals]]
171 # Other Scalable Vector ISAs
174 <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
175 * NEC SX Aurora (still in production, inspired by Cray)
176 <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>
177 * RISC-V RVV (inspired by Cray)
178 <https://github.com/riscv/riscv-v-spec>
179 * MRISC32 ISA Manual (under active development)
180 <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
181 * Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from
184 A comprehensive list of 3D GPU, Packed SIMD, Predicated-SIMD and true Scalable
185 Vector ISAs may be found at the [[sv/vector_isa_comparison]] page.
186 Note: AVX-512 and SVE2 are *not strict Vector ISAs*, they are Predicated-SIMD.
187 *Public discussions have taken place at Conferences attended by both Intel
188 and ARM on adding a `setvl` instruction which would easily make both
189 AVX-512 and SVE2 truly "Scalable".*
191 # Major opcodes summary
193 Simple-V itself only requires five instructions with 6-bit Minor XO
194 (bits 26-31), and the SVP64 Prefix Encoding requires
195 25% space of the EXT001 Major Opcode.
196 There are **no** Vector Instructions and consequently **no further
197 opcode space is required**.
199 That said: for the target workloads for which Scalable Vectors are typically
200 used, the Scalar ISA on which those workloads critically rely
202 The Libre-SOC Team has therefore been addressing that by developing
203 a number of Scalar instructions in specialist areas (Big Integer,
204 Cryptography, 3D, Audio/Video, DSP) and it is these which require
205 considerable Scalar opcode space.
207 Please be advised that even though SV is entirely DRAFT status, there
208 is considerable concern that because there is not yet any two-way
209 day-to-day communication established with the OPF ISA WG, we have
210 no idea if any of these are conflicting with future plans by any OPF
211 Members. **The External ISA WG RFC Process is yet to be ratified
212 and Libre-SOC may not join the OPF as an entity because it does
213 not exist except in name. Even if it existed it would be a conflict
214 of interest to join the OPF, due to our funding remit from NLnet**.
215 We therefore proceed on the basis of making public the intention to
216 submit RFCs once the External ISA WG RFC Process is in place and,
217 in a wholly unsatisfactory manner have to *hope and trust* that
218 OPF ISA WG Members are reading this and take it into consideration.
220 **None of these Draft opcodes are intended for private custom
221 secret proprietary usage. They are all intended for entirely
222 public, upstream, high-profile mass-volume day-to-day usage at the
223 same level as add, popcnt and fld**
225 * SVP64 requires 25% of EXT01 (bits 6 and 9 set to 1)
226 * bitmanip requires two major opcodes (due to 16+ bit immediates)
227 those are currently EXT022 and EXT05.
228 * brownfield encoding in one of those two major opcodes still
229 requires multiple VA-Form operations (in greater numbers
230 than EXT04 has spare)
231 * space in EXT019 next to addpcis and crops is recommended
232 (or any 5-6 bit Minor XO areas)
233 * many X-Form opcodes currently in EXT022 have no preference
234 for a location at all, and may be moved to EXT059, EXT019,
235 EXT031 or other much more suitable location.
237 Note that there is no Sandbox allocation in the published ISA Spec for
238 v3.1 EXT01 usage, and because SVP64 is already 64-bit Prefixed,
239 Prefixed-Prefixed-instructions (SVP64 Prefixed v3.1 Prefixed)
240 would become a whopping 96-bit long instruction. Avoiding this
241 situation is a high priority which in turn by necessity puts pressure
242 on the 32-bit Major Opcode space.
244 Note also that EXT022, the Official Architectural Sandbox area
245 is under severe design pressure as it is insufficient to hold
246 the full extent of the instruction additions required to create
247 a Hybrid 3D CPU-VPU-GPU.
249 **Whilst SVP64 is only 5 instructions
250 the heavy focus on VSX for the past 12 years has left the SFFS Level
251 anaemic and out-of-date compared to ARM and x86. This is partially
252 a blessing as the Scalar ISA has remained clean. Approximately
253 100 additional (optional) Scalar Instructions are up for proposal to bring SFFS
258 Examples experiments future ideas discussion:
260 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
261 * [[sv/masked_vector_chaining]]
263 * [[sv/example_dep_matrices]]
264 * [[sv/major_opcode_allocation]]
266 * [[sv/16_bit_compressed]] experimental
267 * [[sv/toc_data_pointer]] experimental
268 * [[sv/predication]] discussion on predication concepts
269 * [[sv/register_type_tags]]
270 * [[sv/mv.x]] deprecated in favour of Indexed REMAP
274 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
275 * [[sv/vector_isa_comparison]] - a list of Packed SIMD, GPU,
276 and other Scalable Vector ISAs
277 * [[simple_v_extension]] old (deprecated) version
278 * [[openpower/sv/llvm]]