openpower/sv.mdwn

   1 [[!tag standards]]
   2
   3 # Simple-V Vectorisation for the OpenPOWER ISA
   4
   5 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
   6
   7 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
   8
   9 Fundamental design principles:
  10
  11 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
  12 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
  13 * Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions
  14   (termed "preserving Program Order")
  15 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
  16 * Does not modify or deviate from the underlying scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
  17 * Designed for Supercomputing: avoids creating significant sequential
  18 dependency hazards, allowing high performance superscalar microarchitectures to be deployed.
  19
  20 Advantages of these design principles:
  21
  22 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
  23 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
  24 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
  25 * Completely wipes not just SIMD opcode proliferation off the
  26   map (SIMD is O(N^6) opcode proliferation)
  27   but off of Vectorisation ISAs as well.  No more separate Vector
  28   instructions.
  29
  30 Pages being developed and examples
  31
  32 * [[sv/overview]] explaining the basics.
  33 * [[sv/implementation]] implementation planning and coordination
  34 * [[sv/svp64]] contains the packet-format *only*
  35 * [[sv/setvl]] the Cray-style "Vector Length" instruction
  36 * [[sv/cr_int_predication]] instructions needed for effective predication
  37 * [[opcode_regs_deduped]]
  38 * [[sv/vector_swizzle]]
  39 * [[sv/vector_ops]]
  40 * [[sv/mv.swizzle]]
  41 * [[sv/mv.x]]
  42 * SVP64 "Modes":
  43   - For condition register operations see [[sv/cr_ops]] - SVP64 Condition Register ops: Guidelines
  44  on Vectorisation of any v3.0B base operations which return
  45  or modify a Condition Register bit or field.
  46   - For LD/ST Modes, see [[sv/ldst]].
  47   - For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch behaviour: All/Some Vector CRs
  48   - For arithmetic and logical, see [[sv/normal]]
  49 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
  50 * [[sv/fclass]] detect class of FP numbers
  51 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
  52 * [[sv/mv.vec]] move to and from vec2/3/4
  53 * [[sv/sprs]] SPRs
  54 * [[sv/bitmanip]]
  55 * [[sv/biginteger]] Operations that help with big arithmetic
  56 * [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
  57 * [[sv/svstep]] Key stepping instruction for Vertical-First Mode
  58 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
  59 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
  60 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
  61 * Twin targetted instructions (two registers out, one implicit)
  62   Explanation of the rules for twin register targets
  63   (implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
  64   - [[isa/svfixedarith]]
  65   - [[isa/svfparith]]
  66 * TODO: OpenPOWER [[openpower/transcendentals]]
  67
  68 Examples experiments ideas discussion:
  69
  70 * [[sv/masked_vector_chaining]]
  71 * [[sv/discussion]]
  72 * [[sv/example_dep_matrices]]
  73 * [[sv/major_opcode_allocation]]
  74 * [[sv/byteswap]]
  75 * [[sv/16_bit_compressed]] experimental
  76 * [[sv/toc_data_pointer]] experimental
  77 * [[sv/predication]] discussion on predication concepts
  78 * [[sv/register_type_tags]]
  79
  80 Additional links:
  81
  82 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
  83 * [[simple_v_extension]] old (deprecated) version
  84 * [[openpower/sv/llvm]]
  85 * [[openpower/sv/effect-of-more-decode-stages-on-reg-renaming]]
  86
  87 ===
  88
  89 Required Background Reading:
  90 ============================
  91
  92 These are all, deep breath, basically... required reading, *as well as and in addition* to a full and comprehensive deep technical understanding of the Power ISA, in order to understand the depth and background on SVP64 as a 3D GPU and VPU Extension.
  93
  94 I am keenly aware that each of them is 300 to 1,000 pages (just like the Power ISA itself).
  95
  96 This is just how it is.
  97
  98 Given the sheer overwhelming size and scope of SVP64 we have gone to CONSIDERABLE LENGTHS to provide justification and rationalisation for adding the various sub-extensions to the Base Scalar Power ISA.
  99
 100 * Scalar bitmanipulation is justifiable for the exact same reasons the extensions are justifiable for other ISAs.  The additional justification for their inclusion where some instructions are already (sort-of) present in VSX is that VSX is not mandatory, and the complexity of implementation of VSX is too high a price to pay at the Embedded SFFS Compliancy Level.
 101
 102 * Scalar FP-to-INT conversions, likewise.  ARM has a javascript conversion instruction, Power ISA does not (and it costs a ridiculous 45 instructions to implement, including 6 branches!)
 103
 104 * Scalar Transcendentals (SIN, COS, ATAN2, LOG) are easily justifiable for High-Performance Compute workloads.
 105
 106 It also has to be pointed out that normally this work would be covered by multiple separate full-time Workgroups with multiple Members contributing their time and resources!
 107
 108 Overall the contributions that we are developing take the Power ISA out of the specialist highly-focussed market it is presently best known for, and expands it into areas with much wider general adoption and broader uses.
 109
 110
 111 ---
 112
 113 OpenCL specifications are linked here, these are relevant when we get to a 3D GPU / High Performance Compute ISA WG RFC:
 114 [[openpower/transcendentals]]
 115
 116 (Failure to add Transcendentals to a 3D GPU is directly equivalent to *willfully* designing a product that is 100% destined for commercial failure.)
 117
 118 I mention these because they will be encountered in every single commercial GPU ISA, but they're not part of the "Base" (core design) of a Vector Processor. Transcendentals can be added as a sub-RFC.
 119
 120 ---
 121
 122 Actual 3D GPU Architectures and ISAs:
 123 -------------------------------------
 124
 125 * Broadcom Videocore
 126   <https://github.com/hermanhermitage/videocoreiv>
 127
 128 * Etnaviv
 129   <https://github.com/etnaviv/etna_viv/tree/master/doc>
 130
 131 * Nyuzi
 132   <http://www.cs.binghamton.edu/~millerti/nyuziraster.pdf>
 133
 134 * MALI
 135   <https://github.com/cwabbott0/mali-isa-docs>
 136
 137 * AMD
 138   <https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf>
 139   <https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf>
 140
 141 * MIAOW which is *NOT* a 3D GPU, it is a processor which happens to implement a subset of the AMDGPU ISA (Southern Islands), aka a "GPGPU"
 142   <https://miaowgpu.org/>
 143
 144
 145 Actual Vector Processor Architectures and ISAs:
 146 -----------------------------------------------
 147
 148 * NEC SX Aurora
 149   <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>
 150
 151 * Cray ISA
 152   <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
 153
 154 * RISC-V RVV
 155   <https://github.com/riscv/riscv-v-spec>
 156
 157 * MRISC32 ISA Manual (under active development)
 158   <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
 159
 160 * Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from Mitch on direct contact with him.  It is a different approach from the others, which may be termed "Cray-Style Horizontal-First" Vectorisation.  66000 is a *Vertical-First* Vector ISA.
 161
 162 The term Horizontal or Vertical alludes to the Matrix "Row-First" or "Column-First" technique, where:
 163
 164 * Horizontal-First processes all elements in a Vector before moving on to the next instruction
 165 * Vertical-First processes *ONE* element per instruction, and requires loop constructs to explicitly step to the next element.
 166
 167 Vector-type Support by Architecture
 168 [[!table  data="""
 169 Architecture | Horizontal | Vertical
 170 MyISA 66000  |            | X
 171 Cray         | X          |
 172 SX Aurora    | X          |
 173 RVV          | X          |
 174 SVP64        | X          | X
 175 """]]
 176
 177 ===
 178
 179 Obligatory Dilbert:
 180
 181 <img src="https://assets.amuniversal.com/7fada35026ca01393d3d005056a9545d" width="600" />
 182