1 # Simple-V Vectorisation for the OpenPOWER ISA
3 Fundamental design principles:
5 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
6 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
7 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
9 Advantages of these design principles:
11 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
12 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
13 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
15 Pages being developed and examples
17 * [[openpower/sv/predication]]
18 * [[simple_v_extension/masked_vector_chaining]]
20 * [[sv/example_dep_matrices]]