openpower/sv.mdwn

   1 [[!tag standards]]
   2
   3 # Simple-V Vectorisation for the OpenPOWER ISA
   4
   5 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
   6
   7 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
   8
   9 Fundamental design principles:
  10
  11 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
  12 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
  13 * Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions
  14   (termed "preserving Program Order")
  15 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
  16 * Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
  17
  18 Advantages of these design principles:
  19
  20 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
  21 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
  22 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
  23 * Completely wipes not just SIMD opcode proliferation off the
  24   map (SIMD is O(N^6) opcode proliferation)
  25   but off of Vectorisation ISAs as well.  No more separate Vector
  26   instructions.
  27
  28 Pages being developed and examples
  29
  30 * [[sv/overview]] explaining the basics.
  31 * [[sv/implementation]] implementation planning and coordination
  32 * [[sv/predication]] discussion on predication concepts
  33 * [[sv/masked_vector_chaining]]
  34 * [[sv/discussion]]
  35 * [[sv/example_dep_matrices]]
  36 * [[sv/prefix]]
  37 * [[sv/major_opcode_allocation]]
  38 * [[opcode_regs_deduped]]
  39 * [[sv/vector_swizzle]]
  40 * [[sv/mv.swizzle]]
  41 * [[sv/mv.x]]
  42 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
  43 * [[sv/mv.vec]] move to and from vec2/3/4
  44 * [[sv/16_bit_compressed]]
  45 * [[sv/toc_data_pointer]]
  46 * [[sv/cr_int_predication]]
  47 * [[sv/setvl]]
  48 * [[sv/svp64]]
  49 * [[sv/ldst]] Load and Store
  50 * [[sv/sprs]] SPRs
  51 * [[sv/bitmanip]]
  52 * [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
  53 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
  54 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
  55 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
  56 * [[sv/byteswap]]
  57 * TODO: OpenPOWER [[openpower/transcendentals]]
  58
  59 Additional links:
  60
  61 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
  62 * [[simple_v_extension]] old (deprecated) version