5 <img src="https://assets.amuniversal.com/7fada35026ca01393d3d005056a9545d" width="600" />
9 * <https://bugs.libre-soc.org/show_bug.cgi?id=213>
10 * <https://youtu.be/ZQ5hw9AwO1U> walkthrough video (19jun2022)
11 * <https://ftp.libre-soc.org/simple_v_spec.pdf>
12 PDF version of this DRAFT specification
14 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
18 # Scalable Vectors for the Power ISA
20 SV is designed as a strict RISC-paradigm
21 Scalable Vector ISA for Hybrid 3D CPU GPU VPU workloads.
22 As such it brings features normally only found in Cray Supercomputers
23 (Cray-1, NEC SX-Aurora)
24 and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
25 a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
26 explicit Vector opcode exists in SV, at all**. It is suitable for
27 low-power Embedded and DSP Workloads as much as it is for power-efficient
30 Fundamental design principles:
32 * Taking the simplicity of the RISC paradigm and applying it strictly and
33 uniformly to create a Scalable Vector ISA.
34 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar
36 * Preserving the underlying scalar execution dependencies as if the
37 for-loop had been expanded as actual scalar instructions
38 (termed "preserving Program Order")
39 * Augments ("tags") existing instructions, providing Vectorisation
40 "context" rather than adding new instructions.
41 * Strictly does not interfere with or alter the non-Scalable Power ISA
43 * In the Prefix space, does not modify or deviate from the underlying
45 unless it provides significant performance or other advantage to do so
46 in the Vector space (dropping the "sticky" characteristics
47 of XER.SO and CR0.SO for example)
48 * Designed for Supercomputing: avoids creating significant sequential
49 dependency hazards, allowing standard
50 high performance superscalar multi-issue
51 micro-architectures to be leveraged.
52 * Divided into Compliancy Levels to reduce cost of implementation for
55 Advantages of these design principles:
57 * Simplicity of introduction and implementation on top of
58 the existing Power ISA without disruption.
59 * It is therefore easy to create a first (and sometimes only)
60 implementation as literally a for-loop in hardware, simulators, and
62 * Hardware Architects may understand and implement SV as being an
63 extra pipeline stage, inserted between decode and issue, that is
64 a simple for-loop issuing element-level sub-instructions.
65 * More complex HDL can be done by repeating existing scalar ALUs and
66 pipelines as blocks and leveraging existing Multi-Issue Infrastructure
67 * As (mostly) a high-level "context" that does not (significantly) deviate
68 from scalar Power ISA and, in its purest form being "a for loop around
69 scalar instructions", it is minimally-disruptive and consequently stands
70 a reasonable chance of broad community adoption and acceptance
71 * Completely wipes not just SIMD opcode proliferation off the
72 map (SIMD is O(N^6) opcode proliferation)
73 but off of Vectorisation ISAs as well. No more separate Vector
76 Comparative instruction count:
78 * ARM NEON SIMD: around 2,000 instructions, prerequisite: ARM Scalar.
79 * ARM SVE: around 4,000 instructions, prerequisite: NEON.
80 * ARM SVE2: around 1,000 instructions, prerequisite: SVE
81 * Intel AVX-512: around 4,000 instructions, prerequisite AVX, AVX2,
82 AVX-128 and AVX-256 which in turn critically rely on the rest of
83 x86, for a grand total of well over 10,000 instructions.
84 * RISV-V RVV: 192 instructions, prerequisite 96 Scalar RV64GC instructions
85 * SVP64: **five** instructions, 24-bit prefixing of
86 prerequisite SFS (150) or
87 SFFS (214) Compliancy Subsets
89 SV comprises several [[sv/compliancy_levels]] suited to Embedded, Energy
90 efficient High-Performance Compute, Distributed Computing and Advanced
91 Computational Supercomputing. The Compliancy Levels are arranged such
92 that even at the bare minimum Level, full Soft-Emulation of all
93 optional and future features is possible.
97 Pages being developed and examples
99 * [[sv/overview]] explaining the basics.
100 * [[sv/compliancy_levels]] for minimum subsets through to Advanced
102 * [[sv/implementation]] implementation planning and coordination
103 * [[sv/svp64]] contains the packet-format *only*, the [[svp64/appendix]]
104 contains explanations and further details
105 * [[sv/svp64_quirks]] things in SVP64 that slightly break the rules
106 or are not immediately apparent despite the RISC paradigm
107 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
112 * For condition register operations see [[sv/cr_ops]] - SVP64 Condition
113 Register ops: Guidelines
114 on Vectorisation of any v3.0B base operations which return
115 or modify a Condition Register bit or field.
116 * For LD/ST Modes, see [[sv/ldst]].
117 * For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch
118 behaviour: All/Some Vector CRs
119 * For arithmetic and logical, see [[sv/normal]]
120 * [[sv/mv.vec]] pack/unpack move to and from vec2/3/4,
121 actually an RM.EXTRA Mode and a [[sv/remap]] mode
123 Core SVP64 instructions:
125 * [[sv/setvl]] the Cray-style "Vector Length" instruction
126 * svremap, svindex and svshape: part of [[sv/remap]] "Remapping" for
127 Matrix Multiply, DCT/FFT and RGB-style "Structure Packing"
128 as well as Indexing. Also describes associated SPRs.
129 * [[sv/svstep]] Key stepping instruction, primarily for
130 Vertical-First Mode and also providing traditional "Vector Iota"
133 *Please note: there are only five instructions in the whole of SV.
134 Beyond this point are additional **Scalar** instructions related to
135 specific workloads that have nothing to do with the SV Specification*
137 # Optional Scalar instructions
139 **Additional Instructions for specific purposes (not SVP64)**
141 All of these instructions below have nothing to do with SV.
142 They are all entirely designed as Scalar instructions that, as
143 Scalar instructions, stand on their own merit. Considerable
144 lengths have been made to provide justifications for each of these
145 *Scalar* instructions.
147 Some of these Scalar instructions are specifically designed to make
148 Scalable Vector binaries more efficient, such
149 as the crweird group. Others are to bring the Scalar Power ISA
150 up-to-date within specific workloads,
151 such as a Javascript Rounding instruction
152 (which saves 35 instructions includibg 5 branches). None of them are strictly
153 necessary but performance and power consumption may be (or, is already)
155 in certain workloads and use-cases without them.
157 Vector-related but still Scalar:
159 * [[sv/mv.swizzle]] vec2/3/4 Swizzles (RGBA, XYZW) for 3D and CUDA.
160 designed as a Scalar instruction.
161 * [[sv/vector_ops]] scalar operations needed for supporting vectors
162 * [[sv/cr_int_predication]] scalar instructions needed for
163 effective predication
165 Stand-alone Scalar Instructions:
168 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
169 * [[sv/fclass]] detect class of FP numbers
170 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
171 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
172 * TODO: OpenPOWER adaptation [[openpower/transcendentals]]
174 Twin targetted instructions (two registers out, one implicit, just like
177 * [[isa/svfixedarith]]
179 * [[sv/biginteger]] Operations that help with big arithmetic
181 Explanation of the rules for twin register targets
182 (implicit RS, FRS) explained in SVP64 [[svp64/appendix]]
184 # Other Scalable Vector ISAs
186 These Scalable Vector ISAs are listed to aid in understanding and
187 context of what is involved.
190 <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
191 * NEC SX Aurora (still in production, inspired by Cray)
192 <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>
193 * RISC-V RVV (inspired by Cray)
194 <https://github.com/riscv/riscv-v-spec>
195 * MRISC32 ISA Manual (under active development)
196 <https://github.com/mrisc32/mrisc32/tree/master/isa-manual>
197 * Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from
200 A comprehensive list of 3D GPU, Packed SIMD, Predicated-SIMD and true Scalable
201 Vector ISAs may be found at the [[sv/vector_isa_comparison]] page.
202 Note: AVX-512 and SVE2 are *not Vector ISAs*, they are Predicated-SIMD.
203 *Public discussions have taken place at Conferences attended by both Intel
204 and ARM on adding a `setvl` instruction which would easily make both
205 AVX-512 and SVE2 truly "Scalable".*
207 # Major opcodes summary
209 Simple-V itself only requires five instructions with 6-bit Minor XO
210 (bits 26-31), and the SVP64 Prefix Encoding requires
211 25% space of the EXT001 Major Opcode.
212 There are **no** Vector Instructions and consequently **no further
213 opcode space is required**. Even though they are currently
214 placed in the EXT022 Sandbox, the "Management" instructions
215 (setvl, svstep, svremap, svshape, svindex) are designed to fit
216 cleanly into EXT019 (like `addpcis`) or other 5/6-bit Minor
217 XO area that has space for Rc=1.
219 That said: for the target workloads for which Scalable Vectors are typically
220 used, the Scalar ISA on which those workloads critically rely
222 The Libre-SOC Team has therefore been addressing that by developing
223 a number of Scalar instructions in specialist areas (Big Integer,
224 Cryptography, 3D, Audio/Video, DSP) and it is these which require
225 considerable Scalar opcode space.
227 Please be advised that even though SV is entirely DRAFT status, there
228 is considerable concern that because there is not yet any two-way
229 day-to-day communication established with the OPF ISA WG, we have
230 no idea if any of these are conflicting with future plans by any OPF
231 Members. **The External ISA WG RFC Process is yet to be ratified
232 and Libre-SOC may not join the OPF as an entity because it does
233 not exist except in name. Even if it existed it would be a conflict
234 of interest to join the OPF, due to our funding remit from NLnet**.
235 We therefore proceed on the basis of making public the intention to
236 submit RFCs once the External ISA WG RFC Process is in place and,
237 in a wholly unsatisfactory manner have to *hope and trust* that
238 OPF ISA WG Members are reading this and take it into consideration.
242 As in above sections, it is emphasised strongly that Simple-V in no
243 way critically depends on the 100 or so *Scalar* instructions also
244 being developed by Libre-SOC.
246 **None of these Draft opcodes are intended for private custom
247 secret proprietary usage. They are all intended for entirely
248 public, upstream, high-profile mass-volume day-to-day usage at the
249 same level as add, popcnt and fld**
251 * bitmanip requires two major opcodes (due to 16+ bit immediates)
252 those are currently EXT022 and EXT05.
253 * brownfield encoding in one of those two major opcodes still
254 requires multiple VA-Form operations (in greater numbers
255 than EXT04 has spare)
256 * space in EXT019 next to addpcis and crops is recommended
257 (or any other 5-6 bit Minor XO areas)
258 * many X-Form opcodes currently in EXT022 have no preference
259 for a location at all, and may be moved to EXT059, EXT019,
260 EXT031 or other much more suitable location.
261 * even if ratified and even if the majority (mostly X-Form)
262 is moved to other locations, the large immediate sizes of
263 the remaining bitmanip instructions means
264 it would be highly likely these remaining instructions would need two
265 major opcodes. Fortuitously the v3.1 Spec states that
266 both EXT005 and EXT009 are
269 **Additional observations**
271 Note that there is no Sandbox allocation in the published ISA Spec for
272 v3.1 EXT01 usage, and because SVP64 is already 64-bit Prefixed,
273 Prefixed-Prefixed-instructions (SVP64 Prefixed v3.1 Prefixed)
274 would become a whopping 96-bit long instruction. Avoiding this
275 situation is a high priority which in turn by necessity puts pressure
276 on the 32-bit Major Opcode space.
278 SVP64 itself is already under pressure, being only 24 bits. If it is
279 not permitted to take up 25% of EXT001 then it would have to be proposed
280 in its own Major Opcode, which on first consideration would be beneficial
281 for SVP64 due to the availability of 2 extra bits.
282 However when combined with the bitmanip scalar instructions
283 requiring two Major opcodes this would come to a grand total of 3 precious
284 Major opcodes. On balance, then, sacrificing 25% of EXT001 is the "least
287 Note also that EXT022, the Official Architectural Sandbox area
288 available for "Custom non-approved purposes" according to the Power
290 is under severe design pressure as it is insufficient to hold
291 the full extent of the instruction additions required to create
292 a Hybrid 3D CPU-VPU-GPU. Akthough the wording of the Power ISA
293 Specification leaves open the *possibility* of not needing to
294 propose ISA Extensions to the ISA WG, it is clear that EXT022
295 is an inappropriate location for a large high-profile Extension
296 intended for mass-volume product deployment. Every in-good-faith effort will
297 therefore be made to work with the OPF ISA WG to
298 submit SVP64 via the External RFC Process.
300 **Whilst SVP64 is only 5 instructions
301 the heavy focus on VSX for the past 12 years has left the SFFS Level
302 anaemic and out-of-date compared to ARM and x86.**
304 a blessing, as the Scalar ISA has remained clean, making it
305 highly suited to RISC-paradigm Scalable Vector Prefixing. Approximately
306 100 additional (optional) Scalar Instructions are up for proposal to bring SFFS
307 up-to-date. None of them require or depend on PackedSIMD VSX (or VMX).
311 Examples experiments future ideas discussion:
313 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
314 * [[sv/masked_vector_chaining]]
316 * [[sv/example_dep_matrices]]
317 * [[sv/major_opcode_allocation]]
319 * [[sv/16_bit_compressed]] experimental
320 * [[sv/toc_data_pointer]] experimental
321 * [[sv/predication]] discussion on predication concepts
322 * [[sv/register_type_tags]]
323 * [[sv/mv.x]] deprecated in favour of Indexed REMAP
327 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
328 * [[sv/vector_isa_comparison]] - a list of Packed SIMD, GPU,
329 and other Scalable Vector ISAs
330 * [[simple_v_extension]] old (deprecated) version
331 * [[openpower/sv/llvm]]