openpower/sv.mdwn

   1 # Simple-V Vectorisation for the OpenPOWER ISA
   2
   3 Fundamental design principles:
   4
   5 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
   6 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
   7 * Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions.
   8 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
   9 * Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)
  10
  11 Advantages of these design principles:
  12
  13 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
  14 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
  15 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
  16
  17 Pages being developed and examples
  18
  19 * [[sv/predication]]
  20 * [[sv/masked_vector_chaining]]
  21 * [[sv/discussion]]
  22 * [[sv/example_dep_matrices]]
  23 * [[sv/prefix]]
  24 * [[sv/major_opcode_allocation]]
  25 * [[opcode_regs_deduped]]