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[libreriscv.git] / openpower / sv.mdwn
1 # Simple-V Vectorisation for the OpenPOWER ISA
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3 Fundamental design principles:
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5 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
6 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
7 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
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9 Advantages of these design principles:
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11 * It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
12 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
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14 Pages being developed and examples
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16 * [[openpower/sv/predication]]
17 * [[simple_v_extension/masked_vector_chaining]]
18 * [[sv/discussion]]