openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * [[openpower/isatables]]
   8 * https://forums.raptorcs.com/
   9 * http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
  10 * http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo
  11 * http://bugs.libre-riscv.org/show_bug.cgi?id=179
  12 * https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
  13 * https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
  14
  15 Summary
  16
  17 * FP32 is converted to FP64. Requires SimpleV to be active.
  18 * FP16 needed
  19 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  20 * FCVT between 16/32/64 needed
  21 * c++11 atomics not very efficient
  22 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  23 * needs escape sequencing (ISAMUX/NS)
  24
  25 # What we are *NOT* doing:
  26
  27 * A processor that is fundamentally incompatible (noncompliant) with Power.
  28  (**escape-sequencing requires and guarantees compatibility**).
  29 * Opcode 4 Signal Processing (SPE)
  30 * Opcode 4 Vectors or Opcode 60 VSX
  31 * Avoidable legacy opcodes
  32
  33 # SimpleV
  34
  35 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  36 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  37 register files to "a sequence of elements".  The **one** instruction
  38 (an unmodified **scalar** instruction) is interpreted as a *hardware
  39 for-loop* that issues **multiple** internal instructions with
  40 sequentially-incrementing register numbers.
  41
  42 Thus it is completely unnecessary to add any vector opcodes - at all -
  43 saving hugely on both hardware and compiler development time when
  44 the concept is dropped on top of a pre-existing ISA.
  45
  46 # Integer Overflow / Saturate
  47
  48 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  49
  50 # atomics
  51
  52 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  53
  54 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  55
  56 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  57
  58 # FP16
  59
  60 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  61
  62 Usually done with a fmt field, 2 bit, last one is FP128
  63
  64 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  65
  66 # Escape Sequencing
  67
  68 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  69 from OpenPower Foundation.
  70
  71 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  72 (including for and by OpenPower Foundation)
  73
  74 ## Branches in namespaces
  75
  76 Branches are fine as it is up to the compiler to decide whether to let the
  77 ISAMUX/NS/escape-sequence countdown run out.
  78
  79 This is all a software / compiler / ABI issue.
  80
  81 ## Function calls in namespaces
  82
  83 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  84
  85 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  86
  87 All of this is a software issue (compiler / ABI).
  88
  89 # Compressed, 48, 64, VBLOCK
  90
  91 TODO investigate Power VLE (Freescale doc Ref 314-68105)
  92
  93 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
  94 entire row, 2 bits instead of 3.  greatly simplifies decoder.
  95
  96 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
  97 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
  98 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
  99 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 100
 101 # Compressed 16
 102
 103 Further "escape-sequencing".
 104
 105 Only 11 bits available. Idea: have "pages" where one instruction selects
 106 the page number. It also specifies for how long that page is activated
 107 (terminated on a branch)
 108
 109 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 110
 111 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 112
 113 Store activation length in a CSR.
 114
 115 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 116
 117 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 118
 119 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 120
 121 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 122
 123 # RISCV userspace
 124
 125 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 126
 127 the exception entry point:
 128 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 129
 130 the rest of the context switch code is in a different file:
 131 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589