3 EULA released! looks good.
7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
8 * [[openpower/isatables]]
9 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
11 * [[openpower/pearpc]]
12 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
13 * [[3d_gpu/architecture/decoder]]
14 * <https://forums.raptorcs.com/>
15 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
16 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
17 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
18 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
19 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
23 * <https://github.com/lioncash/DolphinPPCTests>
24 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
28 * FP32 is converted to FP64. Requires SimpleV to be active.
30 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
31 * FCVT between 16/32/64 needed
32 * c++11 atomics not very efficient
33 * no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
34 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
36 # What we are *NOT* doing:
38 * A processor that is fundamentally incompatible (noncompliant) with Power.
39 (**escape-sequencing requires and guarantees compatibility**).
40 * Opcode 4 Signal Processing (SPE)
41 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
42 * Avoidable legacy opcodes
46 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
47 SimpleV: a "hardware for-loop" which involves type-casting (both) the
48 register files to "a sequence of elements". The **one** instruction
49 (an unmodified **scalar** instruction) is interpreted as a *hardware
50 for-loop* that issues **multiple** internal instructions with
51 sequentially-incrementing register numbers.
53 Thus it is completely unnecessary to add any vector opcodes - at all -
54 saving hugely on both hardware and compiler development time when
55 the concept is dropped on top of a pre-existing ISA.
57 ## Condition Registers
59 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
63 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
65 # Integer Overflow / Saturate
67 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
71 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
73 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
75 Hot loops contain significant instruction count, really need new c++11 atomics. To be proposed as new extension because other OpenPower members will need them too
79 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
81 Usually done with a fmt field, 2 bit, last one is FP128
83 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise. can also be done as C instruction, only needs 4 bits to specify.
87 aka "ISAMUX/NS". Absolutely critical, also to have official endorsement
88 from OpenPower Foundation.
90 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
91 (including for and by OpenPower Foundation)
93 ## Branches in namespaces
95 Branches are fine as it is up to the compiler to decide whether to let the
96 ISAMUX/NS/escape-sequence countdown run out.
98 This is all a software / compiler / ABI issue.
100 ## Function calls in namespaces
102 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
104 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
106 All of this is a software issue (compiler / ABI).
108 # Compressed, 48, 64, VBLOCK
110 TODO investigate Power VLE (Freescale doc Ref 314-68105)
112 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
113 entire row, 2 bits instead of 3. greatly simplifies decoder.
115 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
116 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
117 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
118 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
120 Note that this requires BE instruction encoding (separate from
121 data BE/LE encoding). BE encoding always places the major opcode in
122 the first 2 bytes of the raw (uninterpreted) sequential instruction
125 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
126 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
127 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
129 It is not possible to distinguish LE-encoded 32-bit instructions
130 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
131 instructions, the opcode falls into:
133 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
134 byte stream for a 32-bit instruction
135 * bytes 0 and 1 for a 16-bit Compressed instruction
136 * bytes 4 and 5 for a 48-bit SVP P48
137 * bytes 6 and 7 for a 64-bit SVP P64
139 Clearly this is an impossible situation, therefore BE is the only
140 option. Note: *this is completely separate from BE/LE for data*
144 Further "escape-sequencing".
146 Only 11 bits available. Idea: have "pages" where one instruction selects
147 the page number. It also specifies for how long that page is activated
148 (terminated on a branch)
150 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
152 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
154 Store activation length in a CSR.
156 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
158 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
160 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
162 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
166 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
168 the exception entry point:
169 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
171 the rest of the context switch code is in a different file:
172 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>