openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
   8 * [[openpower/isatables]]
   9 * [[openpower/gem5]]
  10 * [[openpower/pearpc]]
  11 * [[3d_gpu/architecture/decoder]]
  12 * <https://forums.raptorcs.com/>
  13 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  14 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  15 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  16 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  17 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  18
  19 Summary
  20
  21 * FP32 is converted to FP64. Requires SimpleV to be active.
  22 * FP16 needed
  23 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  24 * FCVT between 16/32/64 needed
  25 * c++11 atomics not very efficient
  26 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  27 * needs escape sequencing (ISAMUX/NS)
  28
  29 # What we are *NOT* doing:
  30
  31 * A processor that is fundamentally incompatible (noncompliant) with Power.
  32  (**escape-sequencing requires and guarantees compatibility**).
  33 * Opcode 4 Signal Processing (SPE)
  34 * Opcode 4 Vectors or Opcode 60 VSX
  35 * Avoidable legacy opcodes
  36
  37 # SimpleV
  38
  39 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  40 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  41 register files to "a sequence of elements".  The **one** instruction
  42 (an unmodified **scalar** instruction) is interpreted as a *hardware
  43 for-loop* that issues **multiple** internal instructions with
  44 sequentially-incrementing register numbers.
  45
  46 Thus it is completely unnecessary to add any vector opcodes - at all -
  47 saving hugely on both hardware and compiler development time when
  48 the concept is dropped on top of a pre-existing ISA.
  49
  50 ## Condition Registers
  51
  52 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  53
  54 ## Carry
  55
  56 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  57
  58 # Integer Overflow / Saturate
  59
  60 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  61
  62 # atomics
  63
  64 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  65
  66 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  67
  68 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  69
  70 # FP16
  71
  72 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  73
  74 Usually done with a fmt field, 2 bit, last one is FP128
  75
  76 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  77
  78 # Escape Sequencing
  79
  80 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  81 from OpenPower Foundation.
  82
  83 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  84 (including for and by OpenPower Foundation)
  85
  86 ## Branches in namespaces
  87
  88 Branches are fine as it is up to the compiler to decide whether to let the
  89 ISAMUX/NS/escape-sequence countdown run out.
  90
  91 This is all a software / compiler / ABI issue.
  92
  93 ## Function calls in namespaces
  94
  95 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  96
  97 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  98
  99 All of this is a software issue (compiler / ABI).
 100
 101 # Compressed, 48, 64, VBLOCK
 102
 103 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 104
 105 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 106 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 107
 108 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 109 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 110 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 111 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 112
 113 # Compressed 16
 114
 115 Further "escape-sequencing".
 116
 117 Only 11 bits available. Idea: have "pages" where one instruction selects
 118 the page number. It also specifies for how long that page is activated
 119 (terminated on a branch)
 120
 121 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 122
 123 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 124
 125 Store activation length in a CSR.
 126
 127 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 128
 129 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 130
 131 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 132
 133 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 134
 135 # RISCV userspace
 136
 137 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 138
 139 the exception entry point:
 140 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 141
 142 the rest of the context switch code is in a different file:
 143 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589