openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 * https://forums.raptorcs.com/
   6 * http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
   7 * http://bugs.libre-riscv.org/show_bug.cgi?id=179
   8
   9 * FP32 is converted to FP64. Requires SV to be active.
  10 * FP16 needed
  11 * FCVT between 16/32/64 needed
  12 * c++11 atomics not very efficient
  13 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  14 * needs escape sequencing (ISAMUX/NS)
  15
  16 # atomics
  17
  18 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  19
  20 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  21
  22 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  23
  24 # FP16
  25
  26 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  27
  28 Usually done with a fmt field, 2 bit, last one is FP128
  29
  30 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  31
  32 # Escape Sequencing
  33
  34 Absolutely critical, also to have official endorsement from OpenPower Foundation.
  35
  36 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  37
  38 # Compressed, 48, 64, VBLOCK
  39
  40 TODO investigate Power VLE (Freescale doc Ref 314-68105)
  41
  42 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the entire row, 2 bits instead of 3.
  43
  44 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
  45 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
  46 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
  47 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
  48
  49 # Compressed 16
  50
  51 Only 11 bits. Idea: have "pages" where one instruction selects the page number. It also specifies for how long that page is activated (terminated on a branch)
  52
  53 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
  54
  55 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
  56
  57 Store activation length in a CSR.
  58
  59 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
  60
  61 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
  62
  63 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
  64
  65 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
  66
  67 ## Branches
  68
  69 Branches are fine as it is up to the compiler to decide whether to let the countdown run out.
  70
  71 This is all a software / compiler / ABI issue.
  72
  73 ## Function calls.
  74
  75 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  76
  77 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  78
  79 All of this is a software issue (compiler / ABI).
  80
  81 # RISCV userspace
  82
  83 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
  84
  85 the exception entry point:
  86 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
  87
  88 the rest of the context switch code is in a different file:
  89 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589