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[libreriscv.git] / openpower.mdwn
1 # Evaluation
2
3 * FP32 is converted to FP64. Requires SV to be active.
4 * FP16 needed
5 * FCVT between 16/32/64 needed
6 * c++11 atomics not very efficient
7 * no 16/48/64 opcodes, needs a shuffle of opcodes
8 * needs escape sequencing (ISAMUX/NS)